{"id":19714,"date":"2024-03-18T09:55:52","date_gmt":"2024-03-18T09:55:52","guid":{"rendered":"https:\/\/chipedge.com\/?p=19714"},"modified":"2025-07-25T18:28:09","modified_gmt":"2025-07-25T18:28:09","slug":"what-is-routing-in-vlsi-physical-design","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/what-is-routing-in-vlsi-physical-design\/","title":{"rendered":"What Is Routing In VLSI Physical Design?"},"content":{"rendered":"<p><span style=\"font-weight: 400;\">Routing in the <\/span><a href=\"https:\/\/chipedge.com\/best-vlsi-training-institute-in-bangalore\/\"><span style=\"font-weight: 400;\">VLSI design course<\/span><\/a><span style=\"font-weight: 400;\"> is making physical connections between signal pins using metal layers. Following Clock Tree Synthesis (CTS) and optimization, the routing step determines the exact pathways for interconnecting standard cells, macros, and I\/O pins. The layout creates electrical connections using metals and vias that are determined by the logical connections in the netlist (i.e.; logical connectivity converted as physical connectivity).<\/span><\/p>\n<p><span style=\"font-weight: 400;\">CTS has information on all the cells, blockages, clock trees, buffers, inverters, and I\/O pins that have been put in. The Routing program uses this data to electrically complete all of the connections defined in the netlist, ensuring that there are no DRC violations. The tool makes all the connections defined in the netlist in a way that:<\/span><\/p>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">The design is completely routed<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">There are minor LVS violations and SI breaches.<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">There should be no or few congestion hotspots.<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">The timing of DRCs and QOR are met.<\/span><\/li>\n<\/ul>\n<h2><b>Mechanism of Routing in VLSI:<\/b><\/h2>\n<p><span style=\"font-weight: 400;\">The routing mechanism establishes the specific pathways for interconnections. This contains the regular cell and macro pins, block boundary pins, and chip boundary pads. The tool includes information about the exact placements of blocks, pins of blocks, and I\/O pads at chip borders after placement and CTS. The utility can also access the logical connections defined by the netlist. Metal and vias are used in the routing stage to build electrical connections in layout to fulfil all connections required by the netlist. The program now depends on some &#8220;Design Rules Checks (DRC)&#8221; to perform the natural linkages.<\/span><\/p>\n<h2><b>What are the steps of routing in VLSI?<\/b><\/h2>\n<p><span style=\"font-weight: 400;\">Each metal layer in a grid-based routing system has its tracks and preferred routing direction, which are described in a unified cell in the standard cell library. Routing activities are divided into four steps:<\/span><\/p>\n<ol>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Global route<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Track Assignment<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Detail Routing<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Search and repair<\/span><\/li>\n<\/ol>\n<h3><b>Global Route:\u00a0<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Global routes assign nets to particular metal layers and global routing cells. The global route aims to avoid crowded global cells while making as few diversions as possible. Global routes also avoid pre-routed P\/G, placement, and routing bottlenecks.<\/span><\/p>\n<h3><b>Track Assignment (TA):<\/b><span style=\"font-weight: 400;\">\u00a0<\/span><\/h3>\n<p><span style=\"font-weight: 400;\">It allocates each net to a certain track and lays down actual metal traces. To reduce the number of vias, it attempts to create long, straight lines. At this stage, physical DRC is not considered.\u00a0<\/span><\/p>\n<h3><b>Detail Routing:\u00a0<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Detail Routing seeks to repair any DRC violations following track assignment using a set size small region (SBox). The detailed routing goes through the whole design box by box until the routing pass is finished. It also performs timing-driven routing.<\/span><\/p>\n<h3><b>Search and Repair:\u00a0<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">This resolves any remaining DRC breaches using many iterative loops with progressively bigger SBox sizes.<\/span><\/p>\n<h2><b>Conclusion<\/b><\/h2>\n<p><span style=\"font-weight: 400;\">If you want to learn more new things about VLSI design, enrol yourself in one of the <\/span><a href=\"https:\/\/chipedge.com\/vlsi-training-online\/\"><span style=\"font-weight: 400;\">VLSI courses online<\/span><\/a><span style=\"font-weight: 400;\"> here at Chipedge, the best <\/span><a href=\"https:\/\/chipedge.com\/best-vlsi-training-institute-in-bangalore\/\"><span style=\"font-weight: 400;\">VLSI training institute<\/span><\/a><span style=\"font-weight: 400;\"> in Bangalore. It offers a wide range of VLSI design courses including design verification courses, RTL design courses, etc. Contact us to know more.<\/span><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Routing in the VLSI design course is making physical connections between signal pins using metal layers. Following Clock Tree Synthesis [&hellip;]<\/p>\n","protected":false},"author":7,"featured_media":25536,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"default","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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