{"id":19454,"date":"2024-02-26T09:56:20","date_gmt":"2024-02-26T09:56:20","guid":{"rendered":"https:\/\/chipedge.com\/?p=19454"},"modified":"2024-02-26T09:56:20","modified_gmt":"2024-02-26T09:56:20","slug":"what-is-latch-up-in-vlsi-and-its-prevention-techniques","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/what-is-latch-up-in-vlsi-and-its-prevention-techniques\/","title":{"rendered":"What is Latch Up in VLSI and Its Prevention Techniques?"},"content":{"rendered":"

Latch-up in VLSI is a short circuit\/low impedance channel generated between the power and ground rails of a MOSFET circuit, resulting in high current leading to IC damage. It is caused by the interaction of parasitic PNP and NPN transistors (BJTs). This results in a structure that resembles a Silicon Controlled Rectifier (SCR). These create a positive feedback loop by short-circuiting the power and ground rails, resulting in excessive current and perhaps causing damage to the device.<\/span><\/p>\n

How Does Latch-Up Form?<\/span><\/h2>\n

The parasitic structure is commonly equivalent to a thyristor (or SCR), a PNPN structure that functions as a PNP and an NPN transistor stacked next to each other. When one of the transistors conducts during a latch-up, the other also begins to conduct.<\/span><\/p>\n

They both maintain saturation for as long as the structure is forward-biased and some current flows through it- which is normal until the power is turned off. The SCR parasitic structure is produced on the output drivers of the gates as a component of the totem-pole PMOS and NMOS transistor pair.<\/span><\/p>\n

What is the Cause for Latch-Up in VLSI?<\/span><\/h2>\n