{"id":10734,"date":"2024-03-14T11:48:00","date_gmt":"2024-03-14T11:48:00","guid":{"rendered":"https:\/\/chipedge.com\/?p=10734"},"modified":"2024-03-14T11:48:00","modified_gmt":"2024-03-14T11:48:00","slug":"steps-in-vlsi-physical-design-flow","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/steps-in-vlsi-physical-design-flow\/","title":{"rendered":"Steps In VLSI Physical Design Flow"},"content":{"rendered":"

VLSI physical design flow is a cardinal process of converting synthesized netlist, design curtailment, and standard library to a layout as per the design rules. This layout is further sent to the foundry for the creation of the chip.<\/span><\/p>\n

According to an article in the <\/span>Times of India<\/span><\/a>, we fit more than 50 billion transistors into a single IC. There is an increasing need for intelligent ICs from the VLSI engineers. Physical design plays a crucial role in the building of ICs. VLSI Design Flow is an algorithm with definite objectives some of which consist of wire length, minimum area, and power optimization. Fundamentally the <\/span>VLSI course<\/span><\/a> starts from where design flow ends.<\/span><\/p>\n

 <\/p>\n

8 Steps Involved in VLSI Physical Design Flow<\/span><\/h2>\n

Step 1: Create a Gate-Level Netlist (After Synthesis)<\/span><\/h3>\n

The netlist is the result of the synthesis process and is the foundation for physical design. Synthesis translates RTL designs written in VHDL or Verilog HDL into gate-level specifications that can be understood by the next set of tools. The cells employed, their interconnections, the area used, and other parameters are all listed in this netlist.<\/span><\/p>\n

Step 2: Partitioning<\/span><\/h3>\n

The next step of partitioning helps to divide the chip into separate chunks. This procedure is performed primarily to distinguish between distinct functional blocks and to facilitate placement and routing. When the design engineer separates the overall design into sub-blocks and then proceeds to design each module during the RTL design course, this is known as partitioning.\u00a0<\/span><\/p>\n

Step 3: Floorplanning<\/span><\/h3>\n

Under this step, we calculate the dimensions of all the blocks and place them in appropriate spots on the chip. This step is performed to keep the blocks that are highly connected close to one another.\u00a0<\/span><\/p>\n

Step 4: Placement<\/span><\/h3>\n

Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell in such a way that the design should have minimal congestion and the best timing. Every PnR tool provides various commands\/switches so that users can optimize the design in a better way in terms of timing, congestion, area, and power as per their requirements. Based on the preferences set by the user, the tool tray is placed and optimized for better QoR.\u00a0<\/span><\/p>\n

Placement does not place only the standard cells present in the synthesized netlist but also places many physical-only cells and adds buffers\/inverters as per the requirement to meet the timings, DRV, and foundry requirements. Here are the basic steps that the tool performs during the placement and optimization stage.\u00a0<\/span><\/p>\n

Step 5: Static Time Analysis\u00a0\u00a0<\/span><\/h3>\n

Static timing analysis<\/span><\/a> (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input\/output interface.<\/span><\/p>\n

Another way to perform timing analysis is to use dynamic simulation, which determines the full behaviour of the circuit for a given set of input stimulus vectors. Compared to dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit. STA is also more thorough because it checks all timing paths, not just the logical conditions that are sensitized by a set of test vectors. However, STA can only check the timing, not the functionality, of a circuit design.<\/span><\/p>\n

Step 6: Clock Tree Synthesis (CTS)\u00a0\u00a0<\/span><\/h3>\n

Clock Tree Synthesis(CTS) is one of the crucial steps in VLSI design flow. It is used to reduce skew and insertion delay. This step helps distribute the clock evenly among all sequential elements of a design.<\/span><\/p>\n

Step 7:\u00a0 Routing\u00a0\u00a0<\/span><\/h3>\n

Routing helps in making the links between the cells and the blocks. There are two types of routing: global routing and detailed routing. Connections are routed through global routing, which assigns routing resources. It also keeps track of a network’s assignment. Whereas, the actual connections are made by detailed routing.\u00a0<\/span><\/p>\n

Step 8: Physical Verification\u00a0<\/span><\/h3>\n

Physical verification ensures that the produced layout design is valid. This involves ensuring that the layout is correct and includes all technological prerequisites, density verification, cleaning density, etc.<\/span><\/p>\n

 <\/p>\n

Conclusion<\/span><\/h2>\n

VLSI physical design<\/span><\/a> flow is a complicated specialization that has grown in popularity over the last two decades. VLSI engineers have a promising future because they are required to design chips or integrated circuits that are used in nearly every device you use today.ChipEdge is one of the best <\/span>VLSI training institute<\/span><\/a> in Bangalore. With Chipedge\u2019s <\/span>VLSI design course<\/span><\/a> you could learn all about physical design flow.<\/span><\/p>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

VLSI physical design flow is a cardinal process of converting synthesized netlist, design curtailment, and standard library to a layout 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