{"id":10554,"date":"2024-02-14T11:11:16","date_gmt":"2024-02-14T11:11:16","guid":{"rendered":"https:\/\/chipedge.com\/?p=10554"},"modified":"2024-02-14T11:11:16","modified_gmt":"2024-02-14T11:11:16","slug":"what-is-clock-tree-synthesis","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/what-is-clock-tree-synthesis\/","title":{"rendered":"What is Clock Tree Synthesis?"},"content":{"rendered":"

Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a <\/span>VLSI design<\/span><\/a>. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided with the placement data as well as the clock tree limitations as input. Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by inserting buffers\/inverters along the clock routes of an <\/span>ASIC design<\/span><\/a>. As a result, CTS is used to balance the skew and reduce insertion latency. Before Clock Tree Synthesis, all clock pins were driven by a single clock source. Clock tree synthesis includes both clock tree construction and clock tree balance.<\/span><\/p>\n

Clock tree inverters may create a clock tree that maintains the correct transition (duty cycle), and clock tree buffers (CTB) can balance the clock tree to fulfil the skew and latency requirements. To fulfil the space and power limits, fewer clock tree inverters and buffers should be employed.<\/span><\/p>\n

A Clock Tree Can Have Different Structures Such As:<\/h2>\n