{"id":81,"date":"2025-01-08T05:04:17","date_gmt":"2025-01-08T05:04:17","guid":{"rendered":"https:\/\/devopspro.agency\/demo\/chipedge\/resources\/?page_id=81"},"modified":"2026-06-19T13:19:33","modified_gmt":"2026-06-19T13:19:33","slug":"webinars","status":"publish","type":"page","link":"https:\/\/chipedge.com\/resources\/webinars\/","title":{"rendered":"Webinars"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"81\" class=\"elementor elementor-81\">\n\t\t\t\t<div class=\"elementor-element elementor-element-6a25188 e-flex e-con-boxed e-con e-parent\" data-id=\"6a25188\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t<div class=\"elementor-element elementor-element-cb00460 e-con-full e-flex e-con e-child\" data-id=\"cb00460\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-4fc6a7f elementor-widget elementor-widget-heading\" data-id=\"4fc6a7f\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h1 class=\"elementor-heading-title elementor-size-default\">Free VLSI Webinar  <span class=\"db\">Sessions by<span class=\"text-blue\"> Industry Leaders<\/span><\/span><\/h1>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-bb48dda e-con-full e-flex e-con e-child\" data-id=\"bb48dda\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-bec39ed elementor-hidden-desktop elementor-hidden-tablet elementor-widget elementor-widget-image\" data-id=\"bec39ed\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"710\" height=\"605\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Rectangle-5.jpg\" class=\"attachment-large size-large wp-image-504\" alt=\"\" srcset=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Rectangle-5.jpg 710w, https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Rectangle-5-300x256.jpg 300w\" sizes=\"(max-width: 710px) 100vw, 710px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-729dfdb e-flex e-con-boxed e-con e-parent\" data-id=\"729dfdb\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t<div class=\"elementor-element elementor-element-f6f0ffa e-con-full e-flex e-con e-child\" data-id=\"f6f0ffa\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-09af2d5 elementor-widget elementor-widget-heading\" data-id=\"09af2d5\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Upcoming <span class=\"text-blue\">Webinars<\/span><\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-37ec566 elementor-widget elementor-widget-shortcode\" data-id=\"37ec566\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"shortcode.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-shortcode\"><p class=\"text-center fw-bold\">No Upcoming Webinars<\/p><\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-c9c46dc e-flex e-con-boxed e-con e-parent\" data-id=\"c9c46dc\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-506e8fc elementor-widget elementor-widget-heading\" data-id=\"506e8fc\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">On Demand <span class=\"text-blue\">Webinars<\/span><\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-02b9707 e-con-full e-flex e-con e-child\" data-id=\"02b9707\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t<div class=\"elementor-element elementor-element-d2685d4 e-con-full e-flex e-con e-child\" data-id=\"d2685d4\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-e119ff5 elementor-widget__width-initial elementor-widget elementor-widget-shortcode\" data-id=\"e119ff5\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"shortcode.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-shortcode\"><div class=\"past-webinar-listing\"><div class=\"row g-4\"><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=TUAV2Up7lzk\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-38021.jpg\" alt=\"Evolution of FPGA Technologies\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>20\/04\/2025<\/span> | <span>10:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=TUAV2Up7lzk\" target=\"_blank\" rel=\"noopener noreferrer\">Evolution of FPGA Technologies<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=ybnzKsbpdVk\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-38027.jpg\" alt=\"Memory Architecture and SRAM cell design\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>29\/06\/2024<\/span> | <span>11:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=ybnzKsbpdVk\" target=\"_blank\" rel=\"noopener noreferrer\">Memory Architecture and SRAM cell design<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=ClcmLYYCsE0\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-38024.jpg\" alt=\"AI \/ ML in Chip Design and Verification\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>18\/05\/2024<\/span> | <span>10:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=ClcmLYYCsE0\" target=\"_blank\" rel=\"noopener noreferrer\">AI \/ ML in Chip Design and Verification<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=pnDY__pb610\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-38018.jpg\" alt=\"The Role of DFT Engineer in SOC Design &#038; Career Opportunities\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>16\/03\/2024<\/span> | <span>10:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=pnDY__pb610\" target=\"_blank\" rel=\"noopener noreferrer\">The Role of DFT Engineer in SOC Design &#038; Career Opportunities<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=khmsfaT_5pg\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-38015.jpg\" alt=\"The Significance of Quality Timing Constraints for ASIC Designs.\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>17\/02\/2024<\/span> | <span>10:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=khmsfaT_5pg\" target=\"_blank\" rel=\"noopener noreferrer\">The Significance of Quality Timing Constraints for ASIC Designs.<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=FFzkLvFzeNA\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-500.jpg\" alt=\"Physical Design &#8211; Part 2: Place &#038; Route Process | Synopsys ICC-II Compiler Tool | Demo (Webinar 2)\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>26\/01\/2023<\/span> | <span>11:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=FFzkLvFzeNA\" target=\"_blank\" rel=\"noopener noreferrer\">Physical Design &#8211; Part 2: Place &#038; Route Process | Synopsys ICC-II Compiler Tool | Demo (Webinar 2)<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/youtube-thumbnail-489.jpg\" alt=\"The Scope and Career Opportunities for Design Verification in Semiconductor (VLSI) Industry\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>26\/01\/2023<\/span> | <span>10:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"\" target=\"_blank\" rel=\"noopener noreferrer\">The Scope and Career Opportunities for Design Verification in Semiconductor (VLSI) Industry<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=KzUDKoCoZxs\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-38012.jpg\" alt=\"The Role Of Physical Design Engineer In VLSI Designs\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>20\/01\/2023<\/span> | <span>10:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=KzUDKoCoZxs\" target=\"_blank\" rel=\"noopener noreferrer\">The Role Of Physical Design Engineer In VLSI Designs<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=zjOtPKm0SP8\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-489.jpg\" alt=\"Physical Design &#8211; Part 1: Synthesis Process | Synopsys Design Compiler Tool | Demo (Webinar 2)\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>06\/01\/2023<\/span> | <span>11:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=zjOtPKm0SP8\" target=\"_blank\" rel=\"noopener noreferrer\">Physical Design &#8211; Part 1: Synthesis Process | Synopsys Design Compiler Tool | Demo (Webinar 2)<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=ldaPT6PB7BU\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-570.jpg\" alt=\"Latest Trends and Challenges in VLSI Physical Design &#038; Career Opportunities\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>26\/12\/2022<\/span> | <span>11:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=ldaPT6PB7BU\" target=\"_blank\" rel=\"noopener noreferrer\">Latest Trends and Challenges in VLSI Physical Design &#038; Career Opportunities<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=Kn2-7EBz_mU\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-589.jpg\" alt=\"VLSI Career Opportunities for ECE\/EEE Students \/ Freshers\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>19\/12\/2022<\/span> | <span>11:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=Kn2-7EBz_mU\" target=\"_blank\" rel=\"noopener noreferrer\">VLSI Career Opportunities for ECE\/EEE Students \/ Freshers<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=S9ZJsIqKpMo\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-588.jpg\" alt=\"The Role &#038; Scope of Design Verification Engineer in VLSI\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>25\/11\/2021<\/span> | <span>11:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=S9ZJsIqKpMo\" target=\"_blank\" rel=\"noopener noreferrer\">The Role &#038; Scope of Design Verification Engineer in VLSI<\/a><\/h3><\/div><\/div><\/div><div class=\"col-lg-4 col-md-6 col-12\"><div class=\"webinar-item h-100\"><div class=\"position-relative webinar-thumb\"><a href=\"https:\/\/www.youtube.com\/watch?v=bvmBZYNsVPw\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/10\/youtube-thumbnail-586.jpg\" alt=\"The Scope &#038; Job Opportunities for Physical Design in VLSI Industry\" class=\"img-fluid webinar-image\"><img decoding=\"async\" \n                            src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\"\n                            alt=\"Play Button\"\n                            class=\"webinar-play-icon position-absolute top-50 start-50 translate-middle\"\n                        ><\/a><\/div><div class=\"webinar-info\"><p class=\"webinar-meta\"><span>29\/05\/2021<\/span> | <span>11:00 am IST<\/span><\/p><h3 class=\"webinar-title-scrl\"><a href=\"https:\/\/www.youtube.com\/watch?v=bvmBZYNsVPw\" target=\"_blank\" rel=\"noopener noreferrer\">The Scope &#038; Job Opportunities for Physical Design in VLSI Industry<\/a><\/h3><\/div><\/div><\/div><\/div><\/div><\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-633a804 e-con-full e-flex e-con e-child\" data-id=\"633a804\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t<div class=\"elementor-element elementor-element-f95c6ad elementor-widget elementor-widget-shortcode\" data-id=\"f95c6ad\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"shortcode.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-shortcode\"><div class=\"blog-listing\"><div class=\"row\"><div class=\"col-md-12\"><div class=\"webinar-post d-flex flex-column justify-content-between\"><div class=\"position-relative\" style=\"width: 100%;\"><a href=\"https:\/\/www.youtube.com\/watch?v=xutgk7kVACc\" target=\"_blank\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2026\/06\/youtube-thumbnail-587.jpg\" alt=\"The Role &#038; Scope of RTL Design Engineer in VLSI Industry &#038; Career Oppurtunities\" class=\"past-img\" style=\"width: 100%; height: 446px; object-fit: cover; object-position: top;\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/Symbol.svg.svg\" class=\"position-absolute top-50 start-50 translate-middle\" style=\"width: 80px; height: 80px;\"><\/a><\/div><div class=\"webinar-content\"><h2 class=\"post-title\"><a href=\"https:\/\/www.youtube.com\/watch?v=xutgk7kVACc\" target=\"_blank\">The Role &#038; Scope of RTL Design Engineer in VLSI Industry &#038; Career Oppurtunities<\/a><\/h2><p class=\"post-meta-min d-flex align-items-center font-20 fw-500\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/webinar-date.svg\" style=\"margin-right: 10px;\"> 05\/06\/2025<span class=\"ms-3 d-flex align-items-center\"><img decoding=\"async\" src=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/02\/webinar-time.svg\" style=\"margin-right: 10px;\"> 11:00 am IST<\/span><\/p><div class=\"about-webinar mt-2\"><p class=\"mb-20 font-16\"> Introduction to RTL Design , Scope of RTL Design in ASIC Flow , Different sign off checks and tools used , Job opportunities in RTL Design<\/p><p class=\"mb-0 font-16\"> <b>Guest Speaker :\u00a0Nutan Agarwal<\/b><\/p><\/div><\/div><\/div><\/div><\/div><\/div><\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Free VLSI Webinar Sessions by Industry Leaders Upcoming Webinars On Demand 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