Synthesis, Signoff STA & LEC (Self-Paced)
About Course
This course comprehensively covers the synthesis, static timing analysis, and LEC, along with videos on lab sessions using Design Compiler, Prime Time and Formality.
How this Course Help in Your Career Growth:
RTL Design/Application/CAD engineers can migrate to Synthesis/STA engineer roles or up-skill themselves to deliver effectively in their current positions.
FPGA engineers can migrate to STA engineer roles.
By acquiring Timing Closure proficiency, PD engineers can significantly improve turn around times of their blocks/designs. This, in turn, will help save valuable working hours as well as open up new growth opportunities.
| Topic No. | Topic Name | Course Contains |
| Topic 1 | Synthesis Flow, Libraries, Coding Guidelines | 2 lecture, 2 Lab – 05:46:00 |
| Topic 2 | Constraining The Design & Optimization | 2 lectures, 2 Lab – 06:53:00 |
| Topic 3 | Scan Insertion & Physical Aware Synthesis | 2 lectures, 2 Lab – 06:25:00 |
| Topic 4 | Low Power Synthesis & LEC | 2 lectures, 2 Lab – 04:59:00 |
| Topic 5 | STA Overview, Exceptions & Post Layout STA | 2 lectures, 2 Lab – 05:24:00 |
| Topic 6 | Multi-corner, Multi-Mode STA, OCV | 2 lectures, 2 Lab – 05:18:00 |
| Topic 7 | Crosstalk and Noise analysis | 2 lectures, 2 Lab – 05:03:00 |
| Topic 8 | Timing Closure, Challenges & techniques | 2 lectures, 2 Lab – 05:28:00 |