RTL Design Online
RTL Design Course comprehensively covers micro architecture, digital design partitioning, RTL Development using synthesis friendly verilog coding styles. Followed by Linting using Spyglass tool, which exhaustively checks various rules and flags errors/warnings for fixing. CDC checks are done with SpyGlass for checking various CDC rules
RTL Design in VLSI covers various rules along with examples and how to analyze, fix them. Each module of RTL Design Online Course has associated hands on labs and multiple projects, to give good exposure to industry complexity.
Synopsys SpyGlass tools is widely used in the industry as sign off tool for LINT, CDC checks.
|Topic No.||Topic Name||Course Contains|
|Topic 1||Verilog Introduction||5 lecture, 5 Lab – 04:57:00|
|Topic 2||ASIC Design Flow||1 lectures, 1 Lab – 01:06:00|
|Topic 3||Synthesis||4 lectures, 4 Lab – 04:12:00|
|Topic 4||Synchronous Designs||3 lectures – 03:12:00|
|Topic 5||Micro Architecture Implementation||2 lectures – 01:46:00|
|Topic 6||RTL Design Good Practices||1 lectures – 01:07:00|
|Topic 7||LINTing 1||2 lectures, 2 Lab – 05:13:00|
|Topic 8||LINTing 2||2 lectures – 05:15:00|
|Topic 9||CDC||2 lectures, 2 Lab – 05:30:00|
|Topic 10||CDC||2 lectures – 02:43:00|
|Topic 11||CDC||3 lectures, 1 Lab – 05:13:00|