RTL Design Online (Self-Learning)

About Course

RTL Design Course comprehensively covers micro architecture, digital design partitioning, RTL Development using synthesis friendly verilog coding styles. Followed by Linting using Spyglass tool, which exhaustively checks various rules and flags errors/warnings for fixing. CDC checks are done with SpyGlass for checking various CDC rules
RTL Design in VLSI covers various rules along with examples and how to analyze, fix them. Each module of RTL Design Online Course has associated hands on labs and multiple projects, to give good exposure to industry complexity.
Synopsys SpyGlass tools is widely used in the industry as sign off tool for LINT, CDC checks.

Course Content:

Topic No.Topic NameCourse Contains
Topic 1Verilog Introduction5 lecture, 5 Lab – 04:57:00
Topic 2ASIC Design Flow  1 lectures, 1 Lab – 01:06:00
Topic 3Synthesis  4 lectures, 4 Lab – 04:12:00
Topic 4Synchronous Designs  3 lectures – 03:12:00
Topic 5Micro Architecture Implementation2 lectures – 01:46:00
Topic 6RTL Design Good Practices  1 lectures – 01:07:00
Topic 7LINTing 12 lectures, 2 Lab – 05:13:00
Topic 8LINTing 2     2 lectures – 05:15:00
Topic 9CDC2 lectures, 2 Lab – 05:30:00
Topic 10CDC 2 lectures – 02:43:00
Topic 11CDC   3 lectures, 1 Lab – 05:13:00

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