Design For Testability -DFT course is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has evolved as a specialization in itself over a period of time. DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.
DFT Course is designed and will be delivered by experts in DFT, as per current industry project requirements. The importance is given to cover the concepts, methodology thoroughly with right emphasis on hands-on training, using Synopsys Design For Testability (DFT) tools with at least 50 % time allocated to lab sessions.