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PLACEMENTS

At ChipEdge, we ensure that our students get placed in the leading companies
and have the best possible opportunities for a great career
in the VLSI industry.

At ChipEdge, we consider the future careers of our students in the VLSI industry as our primary responsibility. With a core team of experts with a combined experience of more than 100 years in VLSI, the ChipEdge placement process is designed to provide the maximum opportunities for students to unlock their potential in VLSI.
The ChipEdge placement process is designed to include

Comprehensive Training in Fundamentals

Every company hiring in VLSI considers a strong foundation in Electronics fundamentals relevant to VLSI as a prerequisite for hiring candidates. ChipEdge provides free online tutorials in the relevant fundamentals as well as regular evaluation tests to ensure that every candidate is ready to crack technical rounds, be it written or verbal.

Soft Skills Training

It is important for candidates to be able to communicate effectively with the interviewers and maintain the required etiquette and body language to be successful in creating an positive impression. Trained soft skills professionals working with the industry are made available to the students to ensure that their corporate communication skills are up to the mark and effective.

Mock Interviews

Industry experts with years of experience hiring candidates for major companies are called upon to provide students with real exposure to how interviews take place. These mock interviews provide the students with honest feedback on areas to improve as well as help to improve their confidence and fluency for actual interviews.

Mentorship by Experts

Students are encouraged to interact with our experienced group of experts and clarify any doubts or confusions regarding their career or the hiring process so as to go for interviews in a clear and confident frame of mind.

Date Student Name Course Company
November 17, 2018 Anil Kumar Swain Physical Design Cadence
October 8, 2018 Rajesh Navuluri Analog Layout Gatelength
September 11, 2018 Bhavya Physical Design Altran
September 7, 2018 Sashank Akula Analog Layout Altran
August 24, 2018 Ashish Mahadu Sontakke Physical Design SYNAPSE
August 17, 2018 Swathi Siddhanti DFT INCISE
July 26, 2018 Anil Kumar A M DFT INCISE
June 25, 2018 Rahul Harali Physical Design SYNAPSE
June 21, 2018 Fazal Hassan Analog Layout UST Global
June 21, 2018 Bhaskar Reddy Boggala Analog Layout UST Global
June 8, 2018 Gargi Deshmukh Physical Design Intel
May 15, 2018 Viresh gavai Analog Layout LeadIC
May 15, 2018 Nanda Khanapur DFT Media Tek
May 15, 2018 Gadde Srikiran DFT Media Tek
April 27, 2018 Bandreddi Venkateshwar Rao Physical Design Aricent
April 27, 2018 Kishor Naik S Physical Design Aricent
April 27, 2018 Manoj Chowdary Physical Design Aricent
April 27, 2018 Payam Nagesh Physical Design Aricent
April 27, 2018 Podila Keerthi Physical Design Aricent
April 27, 2018 Praveen chennam Physical Design Aricent
April 27, 2018 Juturu Muruli Shankar Physical Design Aricent
April 27, 2018 Shreyas BK Physical Design Aricent
April 27, 2018 Jagan Physical Design Wipro
April 25, 2018 Navyatha Physical Design Altran
April 24, 2018 Surabhi R Physical Design Aricent
April 24, 2018 Abhishek Physical Design Aricent
April 24, 2018 Sneha Rathod Physical Design Exiger
April 7, 2018 Neeraj Sharma Physical Design Black Pepper
April 7, 2018 Chaitrashree Analog Layout JGD Tech
April 7, 2018 Prathamesh Kulkarni Analog Layout JGD Tech
April 7, 2018 Shubha P S Analog Layout SibotTechnologies
April 7, 2018 Hemavathy B Physical Design Aricent
April 7, 2018 Suman Physical Design Aricent
April 7, 2018 Jithesh R Physical Design Laksh Semi
April 7, 2018 Anushree Chandran K Physical Design SYNAPSE
March 8, 2018 Shivaraju M A Physical Design SYNAPSE
February 2, 2018 Satyajit Physical Design Ambit

19

Jul'18

Congratulations to two of our Analog Layout students placed in Synopsys

Our esteemed students, Meghana D and Bhaskar Reddy Boggala have been selected by Synopsys. Their hard work and passion for VLSI is the reason for their success in clearing the interview process. The ChipEdge team congratulates them and wishes them all the best in their future endeavours.

Sl.No Date Candidate Name Course Company Placed
1 17-July-18 Meghana D Layout Synopsys
2 17-July-18 Bhaskar Reddy Boggala Layout Synopsys

19

Jul'18

Congratulations to 3 of our DFT students placed in Eximius

Three of our esteemed students,  Venkat Raghav, Manoj Kumar  and Ashok Bellamkonda have been selected by Eximius. Their hard work and passion for VLSI is the reason for their success in clearing the interview process. The ChipEdge team congratulates them and wishes them all the best in their future endeavours.

Sl.No Date Candidate Name Course Company Placed
1 17-July-18 Venkat Raghav DFT Eximius
2 17-July-18 Manoj Kumar DFT Eximius
2 17-July-18 Ashok Bellamkonda DFT Eximius

24

Jun'18

Congratulations to one of our Analog Layout students placed in UST Global

One of our esteemed students, Fazal Hussein have been selected by UST Global. his hard work and passion for VLSI is the reason for their success in clearing the interview process. The ChipEdge team congratulates him and wishes him all the best in his future endeavours.

Sl.No Date Candidate Name Course Company Placed
1 22-July-18 Fazal Hussein Layout UST Global

18

Jun'18

Congratulations to our Analog Layout student placed in Lead IC

Our esteemed student, Viresh Gavai has been selected by Lead IC. HIs hard work and passion for VLSI is the reason for their success in clearing the interview process. The ChipEdge team congratulates him and wishes him all the best in his future endeavours.

Sl.No Date Candidate Name Course Company Placed
1 15 May 18 Viresh gavai Layout Lead IC

18

Jun'18

Congratulations to two of our DFT students placed in MediaTek

Two of our esteemed students, Nanda Khanapur and Gadde Srikiran have been selected by MediaTek. Their hard work and passion for VLSI is the reason for their success in clearing the interview process. The ChipEdge team congratulates them and wishes them all the best in their future endeavours.

10

Jun'18

CONGRATULATION!!! TO Payam Nagesh ,Podila Keerthi ,Praveen chennam , Juturu Muruli Shankar & Shreyas BK at Aricent as PD ENGINEER

Many Congratulations Payam Nagesh ,Podila Keerthi ,Praveen chennam , Juturu Muruli Shankar & Shreyas BK at Aricent as PD ENGINEER.

Payam Nagesh ,Podila Keerthi ,Praveen chennam , Juturu Muruli Shankar & Shreyas BK had 1 year internship experience before joining PD course with ChipEdge. They were very much interested to start his career in VLSI industry. Through friends they came to know about ChipEdge’s high qualityPD training and made a right choice of joining the training.

After completion of the course he got multiple interview opportunities through ChipEdge Placement Cell and ended-up in getting offer from Aricent as PD Engineer.

Their passion and dedication toward his goal and the support from

ChipEdge helped them to reach his goal.

Once again, we congratulate and wish them a best of luck for their career.

Sl.No Date Candidate Name Course Company Placed
1 27th April 18 Payam Nagesh Aricent PD 15
2 27th April 18 Podila Keerthi Aricent PD 13
3 27th April 18 Praveen chennam Aricent PD 14
3 27th April 18 Juturu Muruli Shankar Aricent PD 16
3 27th April 18 Shreyas BK Aricent PD 16

10

Jun'18

Congratulations!!! to Subha P S for being placed at SibotTechnologies as Layout Engineer

Many Congratulations Subha P S for getting Layout Engineer job offers from SibotTechnologies .

Subha P S had 1 year internship experience before joining Layout Engineer course with ChipEdge. They were very much interested to start his career in VLSI industry. Through friends she came to know about ChipEdge’s high quality Layout Engineer training and made a right choice of joining the training. After completion of the course she got multiple interview opportunities through ChipEdge Placement Cell and ended-up in getting offer from SibotTechnologies as Layout Engineer.

Her passion and dedication toward his goal and the support from ChipEdge helped her to reach his goal. Once again, we congratulate and wish her a best of luck for her career..

Sl.No Date Candidate Name Course Company Placed
1 7th April 18 Shubha P S SibotTechnologies CL6

10

Jun'18

CONGRATULATION!!! TO Surabhi R ,Abhishek ,Bandreddi Venkateshwar Rao ,Kishor Naik S & Manoj Chowdary For Getting Placed at Aricent as PD ENGINEER

Many Congratulations Surabhi R ,Abhishek ,Bandreddi Venkateshwar Rao ,Kishor Naik S & Manoj Chowdary at Aricent as PD ENGINEER.

Surabhi R ,Abhishek ,Bandreddi Venkateshwar Rao ,Kishor Naik S & Manoj Chowdary had 1 year internship experience before joining PD  course with ChipEdge. They were very much interested to start his career in VLSI industry. Through friends they came to know about ChipEdge’s high qualityPD training and made a right choice of joining the training.

After completion of the course he got multiple interview opportunities through ChipEdge Placement Cell and ended-up in getting offer from Aricent as PD Engineer.

Their passion and dedication toward his goal and the support from ChipEdge helped them to reach his goal.

Once again, we congratulate and wish them a best of luck for their career.

Sl.No Candidate Name Course Company Placed Batch
1 Surabhi R Physical Design Aricent PD15
2 Abhishek Physical Design Aricent PD15
2 Bandreddi Venkateshwar Rao Physical Design Aricent PD15
4 Kishor Naik S Physical Design Aricent PD15
5 Manoj Chowdary Physical Design Aricent PD15

08

Jun'18

Congratulations!!! to Chaitrashree, Prathamesh for being placed at JGD Tech as Layout Engineer

Many Congratulations Chaitrashree & Prathamesh Kulkarni  for getting Layout Engineer job offers from JGD Tech .

Chaitrashree & Prathamesh Kulkarni had 1 year internship experience before joining Layout Engineer course with ChipEdge. They were very much interested to start his career in VLSI industry. Through friends they came to know about ChipEdge’s high quality Layout Engineer training and made a right choice of joining the training.

After completion of the course he got multiple interview opportunities through ChipEdge Placement Cell and ended-up in getting offer from JGD Tech as Layout Engineer.

Their passion and dedication toward his goal and the support from ChipEdge helped them to reach his goal.

Once again, we congratulate and wish them a best of luck for their career.

Sl.No Date Candidate Name Course Company Placed
1 7 April 18 Chaitrashree Analog Layout JGD Tech
2 7 April 18 Prathamesh Kulkarni Analog Layout JGD Tech

05

Jun'18

Congratulations!!! to Hemavathy B, Suman ,Neeraj

Many Congratulations to our Participants for Accepting Job offers .

After completion of the course these participant’s got multiple interview opportunities through ChipEdge Placement Cell and ended-up in getting offer from the Respective Companies.

Their passion and dedication toward his goal and the support from ChipEdge helped them to reach his goal.

Once again, we congratulate and wish them a best of luck for their career.

Sl.No Date Candidate Name Course Company Placed
1 07-Apr-18 Hemavathy B Physical Design Aricent
2 07-Apr-18 Suman Physical Design Aricent
3 07-Apr-18 Neeraj Sharma Analog Layout Black Pepper
4 07-Apr-18 Jithesh R Physical Design Laksh Semi

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