How to Know Manufacturing Defects Using Design for Testability?

How to Know Manufacturing Defects Using Design for Testability?

Good Chip, Bad Chip

The term “good chip” refers to a chip that has no manufacturing flaws. A manufacturing defect is a finite chip area containing electrically faulty circuitry produced by fabrication faults. These manufacturing defects can be identified using design for testability (DFT). The defects are generally divided into two categories of broad area defects which are also known as global flaws and spot flaws. The yield loss is caused by both sorts of faults but the former occurs on a global scale and includes scratches caused by improper wafer handling or large-area defects caused by mask misalignment. Whereas, the latter results in random local or small flaws resulting from process materials and environmental factors that are most commonly the result of unwanted chemical and airborne particles deposited on the chip at various stages of the process.

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How Can DFT be Used to Identify Manufacturing Defects?

Integrated Circuits design strategies which include testability techniques to a hardware product design are known as design for testability. The new features make it easier to create and apply manufacturing tests to the hardware that has been designed. To ensure that the product hardware is  free of manufacturing defects, design  for testability is used for conducting manufacturing tests. These tests are essential because they could compromise the product’s proper operation.

To identify manufacturing defects using design for testability in VLSI various tests are employed at many stages of the hardware manufacturing process. Run on automatic test equipment (ATE) or, in the case of system maintenance, on the assembled system itself these tests may be able to log diagnostic information regarding the nature of the encountered test fails. Using design for testability for testing manufacturing defects also discovers and alerts the presence of faults. The diagnostic data can be utilised to pinpoint the source of the problem.

Conclusion

In VLSI training, Design for Testability will provide a student with in-depth knowledge of all testability methodologies. DFT techniques aim to reduce the time and effort required to build VLSI circuit test vector sequences and also identify defective chips. ChipEdge, the best VLSI training institute offers all of the online VLSI courses with certificate you’ll need to get started in your career. Register yourself today for the DFT course online.

Sources

https://cdnc.itec.kit.edu/downloads/03_Quality_models_and_Yield_analysis.pdf

https://en.wikipedia.org/wiki/Design_for_testing

https://www.slideshare.net/kumargavanurmath/design-for-testability-65535130

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