Full Time ASIC Design Verification Course starting 22nd October
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Full Time ASIC Design Verification Course starting 24th September
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Full Time ASIC Design Verification Course starting 24th September
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VLSI Courses
Digital VLSI Courses
Physical Design
ASIC Design Verification { FullTime }
Design For Test (DFT)
Synthesis Sign-off STA and LEC
TCL Scripting
Verification using System Verilog
Verification using UVM
Low Power Implementation (PD) using UPF
Analog VLSI Courses
CMOS Analog Circuit Design
High Speed IO Circuit Design
Analog Layout Design
Upcoming New Courses
Analog Mixed Signal (AMS) Verification
Advanced Physical Design
Low Power Design
Advanced DFT
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Physical Design
Batch-11 (Apr-June 2017)
Batch-10 (Jan-Mar 2017)
Batch-9 (July-Oct 2016)
Batch-8 (Apr-June 2016)
Low Power PD
Batch-1 (Jul-Aug 2016)
Synthesis and STA
Batch-5 (Apr-May, 2017)
Batch-4 (Dec ’16 – Feb ’17)
Batch-3 (Sep-Nov, 2016)
DFT
Batch-4 (Jan-Mar 2017)
Batch-3 (Sep-Nov 2016)
Batch-2 (Apr-May 2016)
Analog Layout Design
Batch-5 (Jan-Apr, 2017)
Batch-4 (July-Nov, 2016)
Batch-1,2,3
High Speed IO Design
Batch-1 (Feb–Mar 2017)
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