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DFT – Design For Test

DFT – Design For Test

In the chip design and manufacturing process, DFT or “Design For Test” plays the role of ensuring that each and every node in the chip is manufactured without errors of any kind. This includes designing test features on the chip, generating the required test inputs and outputs, and once the chip is fabricated, testing the chip for errors.

The importance of DFT for chip design and manufacturing companies is in that it helps to avert the huge cost and time delays that will occur if any of the errors are found only after the chip has been shipped to the customer. It is a preventive tool to weed out the defective dies as well as individual packaged units.

DFT is independent of functional verification tests. Functionality tests are required to verify that the chip performs the function it was designed for while DFT checks each and every node irrespective of their functional role, thus ensuring that errors that any manufacturing defects that are missed out in functionality tests are also identified and corrected.

The DFT Flow

Pre-fabrication – before the chip is physically fabricated.

  1. During chip design, DFT architecture is created based on understanding of different blocks on the SoC. This includes adding some extra blocks on the chip to increase its testability.
  2. The functionality of these blocks is then verified.
  3. A link of logic is created which can test each and every node of the chip.
  4. These schemes are verified using simulations.
  5. SCAN/JTAG insertions are performed and ATPG (Automatic Test Pattern Generation) patterns are generated using the appropriate tools.
  6. ATPG patters are simulated and actual outputs during simulations are compared with expected outputs.

Post fabrication – the chip now has to be tested for errors. This is done in two ways

  1. Wafer test – The dies are tested on the wafer itself before they are cut and sorted.
  2. Package Chip test – Individual diesthat have passes the wafer test are then packaged and re-tested with ATPG patterns.

Controllability and Testability

Controllability and testability are the two most important tenets of DFT.

  1. Controllability – The DFT architecture and input should be such that each and every node in the chip can be toggled by the APTG pattern inputs.
  2. Testability – The changes in output corresponding to the toggling of a node should be observable at the packaged part pins.

Scope of DFT in VLSI

Any company which is into silicon chip design requires DFT engineers. Theproportion of DFT engineers in the entire team depends on the type of chip being manufactured, whether it is re-doing an existing chip, adding new functionalities to a chip or creating a new chip altogether. But DFT is a vital process in any VLSI design – DFT engineers and expertize is needed for both product companies like Intel, Broadcom, Qualcomm etc. and in the service companies that support these product companies.

Though the number of DFT engineers in a company will be less than Verification or Physical design engineers, there is a mismatch between the number of DFT engineers needed in the industry and the number of trained engineers. This mismatch is due to the fact that the output of skilled DFT engineers from good institutes or colleges is much less than for the other streams. Hence trained DFT students have an equal opportunity for placement.

Qualifications needed to become a DFT Engineers

Most companies are looking for BE, B-Tech or M-tech students specialized in Electronics. This is because the basic requirement for a DFT profile is a good understanding of Digital Design and CMOS devices. Other than freshers, engineers who have experience in IC testing have an added advantage in shifting to DFT as they already have an understanding of post-silicon testing which is valued by companies. But the majorityof hires in DFT are freshers.

Initial Package and Profile of a DFT Engineer

Service companies have a standard package of around3 l.p.a for freshers. This package is consistent for almost all fields of VLSI like DFT, Verification and PD etc. Due to certain urgent requirement or quality of the candidate this may vary a little but not by much. Those with a testing background might get a higher package.

In product companies, the starting package for the same profile will be around 8-10 l.p.a but the number of vacancies are much less.

Future of a DFT engineer

A DFT engineer with good performance can increase their salary by over three times over a 5 year period be it in a service company or a product company.

Unless one stagnates and does not improve in one’s output and skills, the VLSI industry provides consistent and streamlined growth opportunities.

In product companies, after a few years engineers decide on pursuing career growth either as a technical specialist or move into management. This decision has to be taken keeping one’s strengths, weaknesses and interests in mind. Both these verticals have the same remuneration but different roles within the organization.

Potential for offshore assignments are there once a person has sufficient experience and has moved up the career ladder.

Work Environment

While companies follow a standard 5 day week with perks similar to other professional industries, the VLSI industry requires employees to be willing to work long hours and consecutive days depending on the urgency of the work. During Tape-out, which is when the chip is finally sent for manufacturing, long weeks of 10+ hours of work each day are not uncommon. Unexpected bugs or errors may require the engineers to work at a stretch without much notice.

Leaves and holidays are standard in nature. While product companies have their own set leave calendars, service companies work according to the schedules of their client. VLSI companies normally have an extended holiday season for 10-15 days during the end of the year.

January 3, 2019

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