RTL Signoff with Lint & CDC using SpyGlass

RTL Signoff with Lint &CDC

This VLSI course comprehensively covers the RTL Signoff with lint & CDC and Low Power Cheeks along with hands-on labs using Synopsys SpyGlass Tool. At the end of this course, the candidate will be able to: Review, analyze, and propose changes to improve testability and implement them. Analyze test coverage, propose changes to improve test […]

Physical Design


VLSI Design cycle involves preparing the design for fabrication at a selected foundry (TSMC, Global foundries ..), with a specific technology node (10nm, 7nm..). This process involves several steps starting with floor planning and ending with delivering GDS2 files to foundry after doing all sign off checks. Physical Design has evolved as a complex specialization […]

Verification with System Verilog & UVM

this design verification course is designed and is delivered by practicing experts in Verification, as per the industry requirements. The importance is given to cover the concepts and methodology along with a good emphasis on hands-on training. 60% of the course time is allocated to the guided lab sessions and lab sessions and industry-standard projects.

Analog Circuit Design

The Analog circuit design field has myriad opportunities in various fields-Data converter signal conditioning, Power Management, High-speed interfaces, Instrumentation, etc. job opportunities are available for engineers with a passion for Analog design, strong analytical problem-solving capability, and strong work discipline/commitment.This course is designed for working professionals with at least 1+ years of work experience in […]

Synthesis, Signoff STA & LEC


This VLSI course comprehensively covers the synthesis, static timing analysis, and LEC, along with hands-on labs using Design Compiler, Prime Time and Formality. How this Course Help in Your Career Growth: RTL Design/Application/CAD engineers can migrate to Synthesis/STA engineer roles or up-skill themselves to deliver effectively in their current positions. FPGA engineers can migrate to […]

Design For Test (DFT)

Design for Test -(DFT)

Design For Testability (DFT) is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects.  With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has evolved as a specialization in itself over a period of time. DFT Engineers works on introducing various test […]