ASIC Verification Flow, Verilog Vs SystemVerilog, Testbench Architecture, Migrating from Verilog to System Verilog.
Operations with 4-state Logic, Arrays, Structures, Unions, packed, unpacked, tagged.
Need for Interface, Interface ports, mod ports, clocking, blocks, procedural blocks, Creating Instances, Connecting, DUT and TB via Interfaces.
Fork-join and its controls, Semaphore, Mailbox.
Need for OOPs in testbench, OOPs Terminology, Principles of OOPs, Inheritance, Polymorphysim, Copy (Shallow/Deep copy), Specilized classes, parameterized classes.
Dynamic Arrays, Associative Arrays, Array methods and usage, Tips for scoreboard Development
Need for Randomization, Controlling randomization, Constraints, Inline Constraints, Controlling constraints.
Motivation for UVM, Evolution of UVM, Components in UVM testbench, Creating test stimulus, Phasing in UVM
Introduction to TLM, Ports, exports, implementation, Analysis ports, TLM FIFO, Analysis FIFO, Request-response channel, Sequencer – driver interaction.
Introduction to Factory, Factory overrides, By instance, By type, Uvm resource, Config db, and resource db Sequence, Virtual sequence, Synchronization mechanisms in UVM.
UVM Env Components, Agent, Env, Test, Scoreboard, Monitor, Coverage.
Register Access Layer, Integration with DUT, UVM Tips and Tricks