Design verification Online Course for Working Professionals I ChipEdge

                                                  Admissions are in progress for PD, DFT, RTL Design and ASIC Design Verification Courses

ASIC Design Verification

Get skilled in Verification, the skill set with high number of jobs in VLSI and Achieve Career Growth & Job Satisfaction. Designed & delivered by Verification Experts from VLSI Industry, with Live Online Classes on Weekends.

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  • Expert Trainers

  • Synopsys Tools

  • 100% Money Back Guarantee

  • 24x7 VLSI Lab Access

  • Placement Assistance

  • Start Date29th May 2021
  • Duration:16 Weeks
  • Training Type Instructor Led Live Online

Course Overview

Design Verification (DV) is also called RTL / Functional Verification, which involves testing the Design for Functionality. Verification in VLSI is similar to testing work in software industry. In any VLSI Project, the number of Design Verification Engineers is more than other skill sets. Hence number of job opportunities is more for Verification Engineers. Trained DV Engineers are on demand most of the time. DV Engineers exhaustively test the design (RTL Code) for the functionality and closely work with RTL Design Engineers to get the bugs fixed. Design Verification Course comprehensively covers digital design, Verilog for verification with multiple examples & projects, System Verilog & UVM along with labs & projects.  2 to 3 protocols will be covered during training and part of the projects. The Course is designed and delivered by practicing experts in Verification, as per the industry requirements.  Importance is given to cover the concepts and methodology along with a good emphasis on hands-on training. 60% of the course time is allocated to the guided lab sessions and industry-standard projects.

Course Delivery Model:

Instructor Led Live Online Sessions
Module-specific Lecture sessions and Labs conducted hand-in-hand
Emphasis on hands-on lab sessions aimed at building key skills
Weekdays: Lab support through WhatsApp
Flexible learning with Lab Access from home

Duration & Timings:

For Working Professionals:

  • 16 weeks – ASIC Design Verification Course
  • 9:30 am to 1 pm, Saturday & Sundays
  • These timings are in IST (Indian Standard Timing) time zone.

 

  • The course will be delivered by a Senior VLSI Engineer with lab assistance from a junior VLSI Engineer. Both are currently working in the VLSI industry on the latest technologies.

Knowledge of the below topics is Required.

Working knowledge of Linux.
Knowledge of Digital Design
Working knowledge of Verilog for verification.

You will be able to understand System Verilog, if have the above pre-requisite knowledge.  Online Test on Design Verification with Verilog need to be taken, to assess if you are meeting pre-requisite criteria.

If you do not meet, you need to ramp up using self learning materials/resources or live sessions if available. And take the test again.

Contact our learning advisor for taking the pre-requisite test.

Course Fee

55,999 60,000

  • No Cost EMI option
  • 100% Money Back Guarantee
  • Group Discounts

Speak to our Learning Advisor for details.

VLSI Tools & Lab

Synopsys Tools

VCS Tool Suite.

Technology Libraries To be Used: 14nm Libraries

Lab Access:

  • Flexible learning with online 24×7 lab access running on high-end cloud servers
  • Access VLSI Lab anytime anywhere using VPN

Who Can Attend this Course

  • Freshers who would like to pursue a career in VLSI.
  • Working Professionals (including interns..) from the VLSI / Embedded industry who are currently working in areas like RTL Design, FPGA Design, Board Level Testing and would like to upskill on SV, UVM either  to perform better in current role or  switch your role / career to ASIC Design Verification
  • Professionals from IT / Electronics / Any other sector interested in switching to VLSI industry for career growth.
  • Faculty working in Engineering colleges interested to switch to VLSI industry.

Educational Qualifications

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar

Why Choose ChipEdge ?

Latest VLSI Courses
INDUSTRY RELEVANT COURSES

An exhaustive bouquet of VLSI courses, from Design to Tape-out in both Analog and Digital domains.

Industry experts trainers
EXPERT TRAINERS

A meticulous and stringent selection process in handpicking the best trainers from the industry with good experience & currently working on latest technologies.

Latest Synopsys tools
SYNOPSYS TOOLS

Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.

Individual attention
PLACEMENT ASSISTANCE

Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.

Learning Management system
FLEXIBLE LEARNING MODELS

Multiple Learning Models to choose as per your Learning Needs & budget in most cost effective way.

24x7 Lab access
ONLINE VLSI LAB

Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24x7 availability

Curriculum

ASIC Verification Flow, Verilog Vs SystemVerilog, Testbench Architecture, Migrating from Verilog to System Verilog.

Operations with 4-state Logic, Arrays, Structures, Unions, packed, unpacked, tagged.

Need for Interface, Interface ports, mod ports, clocking, blocks, procedural blocks, Creating Instances, Connecting, DUT and TB via Interfaces.

Fork-join and its controls, Semaphore, Mailbox.

Need for OOPs in testbench, OOPs Terminology, Principles of OOPs, Inheritance, Polymorphysim, Copy (Shallow/Deep copy), Specilized classes, parameterized classes.

Dynamic Arrays, Associative Arrays, Array methods and usage, Tips for scoreboard Development

Need for Randomization, Controlling randomization, Constraints, Inline Constraints, Controlling constraints.

Motivation for UVM, Evolution of UVM, Components in UVM testbench, Creating test stimulus, Phasing in UVM

Introduction to TLM, Ports, exports, implementation, Analysis ports, TLM FIFO, Analysis FIFO, Request-response channel, Sequencer – driver interaction.

Introduction to Factory, Factory overrides, By instance, By type, Uvm resource, Config db, and resource db Sequence, Virtual sequence, Synchronization mechanisms in UVM.

UVM Env Components, Agent, Env, Test, Scoreboard, Monitor, Coverage.

Register Access Layer, Integration with DUT, UVM Tips and Tricks

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Demo Videos

Video Reviews

Learner Reviews

I joined the Design Verification course to get knowledge of verification and job, I met my expectation, trainer was good, good Lab Instructor Support and the best part is 24/7 VPN Support, I experienced very good Lab Experience.

Madhukar Reddy

Awesome experience I had during learning my course. Management is too good they do for candidates at their extent placement is good. Everyone get chance. Happy to be the part of Samsung semiconductor through ChipEdge!

Dhyan Prakash

The course helped me to get industry kind of experience in the dv course. Excellent Trainer. 24/7 VPN access is excellent. The overall experience is fairly good. “Yes” Everything is fine. Training materiel and slides are good.

Sarika S

FAQs

Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge trainers are typically having 10 to 20  years of VLSI industry experience and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor-led online courses on weekends are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by the majority of product / MNC companies in the semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short/long). please check the “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs.  please check with our Course Counsellors.

Course completion certificates will be provided, whoever meets the course completion criteria.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

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