RTL Signoff with Lint, CDC for working Professionals

Last Few days to go for part time DFT Course starting 13th Feb and PD starting 27th Feb

RTL Signoff with Lint & CDC using SpyGlass

Learn from RTL Signoff Expert with 8+ yrs of Industry Experience, using Synopsys Spyglass Tools Suite with 24×7 VLSI Lab Access. Instructor Led Classes on Weekends.

Apply Now
  • Synopsys Tools

  • 100% Money Back Guarantee

  • 24x7 VLSI lab Access.

  • Start Date27th March 2021
  • Duration:6 Weeks
  • Training Type Weekend Online

Course Overview

This VLSI course comprehensively covers the RTL Signoff with lint & CDC and Low Power Cheeks along with hands-on labs using Synopsys SpyGlass Tool.

At the end of this course, the candidate will be able to:

Review, analyze, and propose changes to improve testability and implement them.
Analyze test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
Generate the patterns for both stuck-at and at-speed testing of the design for optimal test cost.
Validate the patterns in a pre-silicon simulation environment
Understanding and applying debugging techniques used in debugging test on silicon in a simulation environment

Course Delivery:

Instructor-Led Online Live Virtual classroom training
Module-specific Lecture sessions and Labs conducted hand-in-hand
Emphasis on Lab driven hands-on training aimed at building key skills
Weekdays: Lab support through Email and WhatsApp
Flexible learning with Lab Access from home through VPN

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session
11.00 am to 11.30 am – Tea Break
11.30 am to 01.00 pm – Lab Session

The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in the VLSI industry on the latest technologies.

At the end of this course, the candidate will be able to:

  • Review, analyze, and propose changes to improve testability and implement them.
  • Analyze test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
  • Generate the patterns for both stuck-at and at-speed testing of the design for optimal test cost.
  • Validate the patterns in a pre-silicon simulation environment
    Understanding and applying debugging techniques used in debugging test on silicon in a simulation environment

Course Fee

24,990 40,000

35% Covid-19 Discount. Exclusive of GST

ENROLL NOW


  • No Cost EMI option
  • 100% Money Back Guarantee
  • Group Discounts

Speak to our Learning Advisor for details.refund policy for more details

VLSI Tools & Lab

Synopsys SpyGlass

Technology Libraries To be Used: 14nm Libraries

Lab Access:

  • Lab Access will be provided through a VPN.
  • Lab can be accessed in 24×7 mode.
  • Weekly 14 hours of Lab access is provided.
  • Can use, allocated usage limit anytime within the week.
  • Additional lab hours per week can be purchased as per your learning needs.
  • Contact our Learning Advisors for details

Who Can Attend

    • M.tech (VLSI) Interns/students, who want to learn Synthesis and Static Timing Analysis.
    • RTL Design, FPGA Design, DFT as well as Physical Design engineers who want to learn Synthesis and STA course thoroughly
  • Synthesis, STA Engineers who want to fill the gaps in their understanding & strengthen STA knowledge to deliver effectively in the current role.
  • CAD / Methodology Engineers or Application Engineers who come across Synthesis and STA in their work.
  • Any working VLSI Engineer seeking to learn Synthesis and STA.

Why Choose ChipEdge ?

Latest VLSI Courses
INDUSTRY RELEVANT COURSES

An exhaustive bouquet of VLSI courses, from Design to Tape-out in both Analog and Digital domains.

Industry experts trainers
EXPERT TRAINERS

A meticulous and stringent selection process in handpicking the best trainers from the industry with good experience & currently working on latest technologies.

Latest Synopsys tools
SYNOPSYS TOOLS

Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.

Individual attention
PLACEMENT ASSISTANCE

Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.

Learning Management system
FLEXIBLE LEARNING MODELS

Multiple Learning Models to choose as per your Learning Needs & budget in most cost effective way.

24x7 Lab access
ONLINE VLSI LAB

Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24x7 availability

Curriculum

  • Purpose of RTL & Linting
  • How does it work?
  • Typical Lint Targets
  • Lint Example
  • SpyGlass Tool Flow
  • SpyGlass Design Read
  • Goal Selection & Setup
  • Run Analysis & Debug
  • SpyGlass Tool Setup
  • CDC Basics
  • Clock Domain & Clock Groups
  • CDC Problems & Solutions
  • CDC Synchronization Techniques
  • Issues in CDC flow
  • Constraints vs Waivers
  • Capturing Design Intent in CDC Constraints
  • SpyGlass Tool setup
  • Run Analysis and Debug

Enquire Now

Demo Videos

Video Reviews

Learner Reviews

FAQs

Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course  will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge trainers are typically having 10 to 20  years of VLSI industry experience and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by the majority of product / MNC companies in the semiconductor(VLSI) industry worldwide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short/long). please check the “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs.  please check with our Course Counsellors.

Course completion certificates will be provided, whoever meets the course completion criteria.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

1 Weeks

×