Physical Design online Course for Working Professionals I ChipEdge

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Physical Design

Learn from Physical Design Expert with 10+ yrs of Industry Experience, using Synopsys Tools  IC Compiler 2, Prime Time, StarRC, IC Validator, with 24×7 VLSI Lab Access.

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  • Integrated Internship

  • Synopsys Tools

  • 100% Money Back Guarantee

  • 24x7 VLSI Lab Access

  • 100% Placement Assistance

  • Start Date3rd October
  • Duration:12 Weeks
  • Training Type Weekend Online

Course Overview

VLSI Design cycle involves preparing the design for fabrication at a selected foundry (TSMC, Global foundries ..), with a specific technology node (10nm, 7nm..). This process involves several steps starting with floor planning and ending with delivering GDS2 files to foundry after doing all sign off checks. Physical Design has evolved as a complex specialization and in-demand skill for the last 2 decades.  This course will give decent exposure to physical design concepts, techniques, along with hands-on labs and a project at the end.

  • Instructor-Led Online Live Training
  • Timings9:30 am to 1 pm (Saturday & Sunday)
  • Module-specific Lecture sessions and Labs conducted hand-in-hand
  • Emphasis on Lab driven hands-on training aimed at building key skills
  • Weekdays: Lab support through WhatsApp
  • Flexible learning with Lab Access from home through VPN

Knowledge of the below topics is Required.

  1. Working knowledge of Linux.
  2. Knowledge of digital Electronics Fundamentals.
  3. Knowledge of CMOS Fundamentals.
  4. Knowledge of Verilog / VHDL is a plus
  5. Knowledge of ASIC / SOC design flow is a plus

Course Fee

40,000 60,000

31% Covid-19 Discount. Exclusive of GST

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ChipEdge believes in quality and professional approach in what we offer, which earned a reputation from industry & professionals.

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VLSI Tools & Lab

  • Physical Design: IC Compiler 2 (ICC2)
  • RC Extraction: Star RC
  • Physical Verification: IC Validator
  • Static Timing Analysis(STA): Prime Time SI

Lab Access:

  • Lab Access will be provided through a VPN.
  • Weekly 14 hours of Lab access is provided.
  • It can be accessed in 24×7 mode.
  • Can use, allocated usage limit anytime within the week

Who Can attend this course

    • B.Tech/M.Tech freshers who have done Internships with any VLSI companies and are interested to improve skills.
    • Working Professionals from the VLSI industry, currently working in some areas (RTL Design, Verification, FPGA Design, Analog Layout, Synthesis, STA, Characterization), but want to switch to Physical design (PD).
    • Working Physical Design Engineers who want to fill the gaps in their understanding & strengthen Physical Design knowledge to deliver effectively in their current role.
    • Working Professionals in Embedded / Electronics (PCB designing, assembling, testing..) and interested in changing Career into the VLSI industry.
    • Faculty working in Engineering Colleges / Universities, teaching VLSI subjects.

Why Chipedge

Latest VLSI Courses
THE LATEST COURSES

An exhaustive bouquet of VLSI courses, from Design to Tape-out in both Analog and Digital domains.

24/7 LAB ACCESS

50% Hands-on Labs, Lab access during non class days and VPN Access to Tools from home.

Job-oriented VLSI Courses for Freshers
THE BEST TRAINERS

A meticulous and stringent selection process in handpicking the best and most qualified trainers from the industry.

Individual Attention
INDIVIDUAL ATTENTION

Limited seats in each batch to ensure individual attention for trainees both in classes and in labs.

Synopsys Tools
SYNOPSYS TOOLS

The latest Synopsys Tools with individual Licenses for each trainee.

LMS
LEARNING MANAGEMENT SYSTEM

Customised Online platform for Content Delivery and Evaluations to achieve a seamless learning experience.

Curriculum

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD flow, contents of each input, qualifying the received inputs and sanity checks.

Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Regioning/Grouping/Bounds.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum routing results.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

One projects will be given covering Netlist to GDS flow. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to complete routing, after cleaning all the issues during sign-off checks.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

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Demo Videos

Videos Reviews

Learner Review

My expectation to join this course was to get into the PD domain and Yes, it met my expectations. The trainer is excellent and he answered all types of queries I asked. The materials provided are good and helped to crack the interviews. After doing this course it helped me to get into PD domain.

Haritha

I Have done a Physical design course in ChipEdge. Mostly all the concepts I learned through practical labs with the help of trainers. Trainers are from product based company with more than 10 years experience. One Good Thing is, they have provided an individual license for all to practice the tool, which has a VPN facility. Through ChipEdge placement assistance, I got placed in Moslogi.

Ajay

My expectations to join this course was to understand complete PD flow, practically implementing the theoretical knowledge of PD and taking the design from RTL to GDSII. The trainer knows in and out of the PD. I just say that I am lucky to get trained by him. The trainer gave equal opportunity to everyone to resolve doubts faced by candidates. Overall, I am satisfied with the course and it met my expectations.

Sadiq

FAQs

Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course  will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge trainers are typically having 10 to 20  years of VLSI industry experience and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short/long). please check the “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs.  please check with our Course Counsellors.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

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