Design For Testability is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, Design For Testability has evolved as a specialization in itself over a period of time. Engineers work on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.
Design for Test course is designed and will be delivered by industry experts in DFT, as per current industry project requirements. In the Design for Test Course the importance is given to cover the concepts, methodology thoroughly with the right emphasis on hands-on training, using Synopsys DFT tools with at least 50 % time allocated to lab sessions.