Course Overview

This design verification course is designed and is delivered by practicing experts in Verification, as per the industry requirements. The importance is given to cover the concepts and methodology along with a good emphasis on hands-on training. 60% of the course time is allocated to the guided lab sessions and lab sessions and industry-standard projects.  

Training Delivery Model

  • Instructor-Led Online Live Virtual classroom training
  • Timings9:30 am to 1 pm (Saturday & Sunday)
  • Module specific Lecture sessions followed by hands-on Lab sessions
  • Weekdays: Lab support through Email and WhatsApp
  • Flexible learning with Lab Access from home through VPN

Training Materials

Soft copies of training materials will be provided, through LMS ( Learning Management System) which can be accessed online any time, any device.

Certification

Course completion certificate will be provided, for all eligible candidates who meet the course completion criteria. The assessment process includes evaluating the assignments and final written test.

Pre-requisites

Knowledge of the below topics is Required.

  • Working knowledge of Linux.
  • Knowledge of Digital Electronics Fundamentals.
  • Knowledge of Verilog and the ability to write Verilog code for a basic digital design using Verilog.

Who Can Attend This Course

  • Working Professionals from VLSI industry who are currently working in some areas (RTL Design, FPGA Design, Synthesis, STA, Board Level Testing and would like to switch their career to ASIC Design Verification.
  • Faculty working in Engineering colleges who would like to understand the VLSI  industry flows and methodologies in Verification.
  • Currently working Electrical engineers who would like to make a career in VLSI verification.

Educational Qualifications

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S  in VLSI / Embedded Systems / Electronics / Similar

Tools to be used

  • Synopsys VCS.

Lab Access

  • Lab Access will be provided through a VPN.
  • Weekly 14 hours of Lab access is provided.
  • It can be accessed in 24×7 mode.
  • Can use, allocated usage limit anytime within the week.

Extra Lab Hours Per Week

  • If you need more than 14 hours of lab access per week, it is possible to provide at extra cost.
  • please get in touch with our course counselors, through Enquiry form

Curriculum

Module 1: Introduction to Basic Verification Flow and need for System Verilog

  • ASIC flow, Verification flow, General Test bench Architecture and Verification plan creation.
  • Overview of HDL and HVL, Need for SystemVerilog, SV capabilities and highlights.

Module 2: System Verilog Basics, Data types

  • New Data types, Arrays, Queues.

Module 3: Interfaces, Processes and Communication

  • Interfaces, Modports, Clocking Blocks, Threads, Fork join , Semaphores, Mailbox.

Module 4: Riding SV on Chariot of OOPs

  • Introduction to OOP concepts of data abstraction, data encapsulation, data hiding, inheritance, and polymorphism.

Module 5: SV Classes and Randomization and constraints

Different randomization techniques and constructs. Inline randomization and constraint blocks.

Module 6: Coverage-based Verification

  • Introduction to code and functional coverage. Functional coverage in SV. Cover groups, cover points, cover bins, and cross-coverage constructs.

Module 7: Faster verification using System Verilog Assertions

  • Introduction to Assertions. Advantages of assertions. Immediate and Concurrent Assertions. Writing assertion Sequences, Different ways of writing Assertions and its constructs and calling methods.Syllabus for online course

Module 8: Verification Methodology, UVM Basics

  • Motivation for UVM, Evolution of UVM, Components in UVM testbench, Creating test stimulus, Phasing in UVM

Module 9: Introduction to TLM Ports

  • Introduction to TLM, Ports, exports, implementation, Analysis ports, TLM FIFO, Analysis FIFO, Request-response channel, Sequencer – driver interaction.

Module 10: Factory and Synchronization mechanisms in UVM

  • Introduction to Factory, Factory overrides, By instance, By type, Uvm resource, Config db, and resource db Sequence, Virtual sequence, Synchronization mechanisms in UVM.

Module 11: UVM Environment Components

UVM Env Components, Agent, Env, Test, Scoreboard, Monitor, Coverage.

Module 12: Register Access Layer and integration with DUT

Register Access Layer, Integration with DUT, UVM Tips and Tricks

Trainer

The trainer is a working professional with hands-on VLSI Verification and training experience of 19+ years.

The trainer is passionate about teaching and has mentored many engineers, both freshers as well as experienced professionals to help them improve their skills, knowledge, and performance. Having led multiple complex projects, she is well abreast of the evolving requirements of the industry.

She is passionate about sharing her knowledge and experiences and at the same time is an excellent communicator who enjoys the challenges of teaching and mentoring the new generation.

Lab Access

  • Weekly 14 hours of Lab access is provided.

Extra Lab Hours Per Week

  • If you need more than 14 hours of lab access per week like 20 / 30 / 40 hrs, it is possible to provide at extra cost.
  • For getting customized lab access, please get in touch with our course counselors, through Enquiry from

Fees

₹ 40,000

Regular Price         ₹ 60,000              + 18% GST

Rs 40,000  without VPN extension after the last day of course work.

Rs 44,000  with VPN extension of 2 weeks after the last day of course work.

No Cost EMI Option Available

Pay in Easy Installments at no extra cost

We accept all Credit/debit cards/net banking/UPI payment Options

Placement Assistance

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

 

100% Money-Back Guarantee

ChipEdge believes in quality and professional approach in what we offer, which earned a reputation from industry & professionals.

Please visit refund policy for more details 

Trainee Video Reviews

Reviews

Frequently Asked Questions (FAQs)

Training is delivered in Instructor Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login into the chipedge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course  will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge  trainers are typically having 10 to 20  years of VLSI industry experience and currently working in latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves. 

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences  is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short / long). please check “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs.  please check with our Course Counsellors. 

Course completion certificates will be provided, whoever meets the course completion criteria.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

Enquire Now
  • 12 WeeksDURATION:
  • November 14, 2020STARTS FROM:

Class Timings

Setup Menus in Admin Panel

X