Course Overview:

This course is designed for working VLSI Engineers  with at least 2+ years of work experience in RTL Design / Verification / FPGA Design and has knowledge of System Verilog.

The course is designed as per the industry requirements and will be delivered by experienced engineers on Design Verification.  Importance is given to cover the concepts, methodology thoroughly with proper emphasis on hands-on labs,  with 40-50% time allocated to lab sessions.

Training Delivery Model:

  • Lecture & Lab sessions go hand in hand, like corporate training.
  • Sessions will be interactive.

Training Material & Certification:

  • Handouts of training material will be provided.
  • Course completion certificate from ChipEdge.
  • Course learning will be assessed as per Bloom’s Taxonomy.

Who Can Attend This Course:

  • Working Professionals from VLSI industry working in areas like RTL Design, Verification, FPGA Design and are interested to learn UVM & build Verification Expertise.
  • Verification / Design Engineers, who have worked or working in Verification using Verilog and used VERA / Specman ..etc. in the past, But want to upgrade to latest Verification Methodologies.
  • Verification Engineers who are conversant with System Verilog, OVM / VMM methodologies and want to learn UVM
  • Faculties working in Engineering Colleges / Universities, teaching VLSI subjects like Verilog / VHDL.


  • Hands on experience in Verification flow.
  • Good knowledge of System Verilog. If you are opting for only UVM course, you need to take an Online Test on System Verilog. Only qualified people are eligible for the course.
  • Knowledge of ASIC / SOC design flow.

Course Content outline:

Each module has associated hands on labs.

Module 1: Verification Methodology, UVM Basics :

Need for a Verification methodology, UVM as a template, introduction, and evolution of UVM. Basic concepts of UVM.

Module 2: UVM Components- Agents, Sequencer, Sequence. Macros, TLM:

 Understanding UVM Test Bench – Objects, Components – Drivers, Sequencers, Sequences, Sequence item, Monitors, transactions, Introduction to Macros, Configuration Database, Resource Database. Introduction to Transaction Level modeling, Concept of TLM in UVM. TLM communications and connections – Interfaces, Ports, Exports, Imps, Analysis Ports, Building a Test Bench for a real-time design with these UVM components.

Module 3: UVM Phasing, UVM Factory, and Advanced sequence control:

 Need for Phasing, Importance of phases and usage of phases in a typical Test Bench environment, Common Phases, Run time phases, User-Defined Phases. Introduction to Factory, Importance of dynamic binding and factory usage. Registering, creating and configuring with Examples. Handling and triggering multiple sequences and sequence body methods efficiently. Virtual Sequences

Module 4: Register Modeling using UVM Register Layer:

 UVM Register Layer, Blocks, Address maps, Register Files, Registers, Fields, DUT Integration – Register Adapter, Register Sequences, Predictor Classes.

Module 5: Reporting, UVCs:

 Reporting in UVM, different verbosity and log controls. Introduction to UVC. Guidelines and rules. UVC environment, UVC layering, Real-time example of UVC.

Module 6: Complete UVC building:

 For a given Design, building a UVC – using best practices, developing fully configurable, reusable UVC and UVM Test Bench environment.

Project Details:

Last two days are dedicated exclusively for the project.

  • To develop UVC and TB for a proprietary/customized/non-standard bus protocol
  • Trainees have to develop the UVC using standard UVM components and develop TEST and test cases to test the UVC and its features
  • Integrate DUT (supplied by trainer)  with UVC/TB and do full verification as per the vplan (supplied by trainer) and collect code coverage.

Tools to be used:

  • Industry standard simulation suite
  • 24×7 lab access through VPN, to enable you to spend more time on labs. This is on top of the Trainer led lab sessions.

Assessment & Certification:

  • Course completion certificate from ChipEdge.
  • At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.


The trainer is a working professional with hands-on VLSI Verification and training experience of 19+ years.

The trainer is passionate about teaching and has mentored many engineers, both freshers as well as experienced professionals to help them improve their skills, knowledge, and performance. Having led multiple complex projects, she is well abreast of the evolving requirements of the industry.

She is passionate about sharing her knowledge and experiences and at the same time is an excellent communicator who enjoys the challenges of teaching and mentoring the new generation.

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