Module 1: Verification Methodology, UVM Basics : Need for a Verification methodology, UVM as a template, introduction and evolution of UVM. Basic concepts of UVM.

Module 2: UVM Components- Agents, Sequencer, Sequence. Macros, TLM: Understanding UVM Test Bench – Objects, Components – Drivers, Sequencers, Sequences, Sequence item, Monitors, transactions, Introduction to Macros, Configuration Database, Resource Database. Introduction to Transaction Level modeling, Concept of TLM in UVM. TLM communications and connections – Interfaces, Ports, Exports, Imps, Analysis Ports, Building test bench for a real time design with these UVM components.

Module 3: UVM Phasing, UVM Factory and Advanced sequence control: Need for Phasing, Importance of phases and usage of phases in a typical Test Bench environment, Common Phases, Run time phases, User-Defined Phases.Introduction to Factory, Importance of dynamic binding and factory usage. Registering , creating and configuring with Examples. Handling and triggering multiple sequences and sequence body methods efficiently. Virtual Sequences

Module 4: Register Modeling using UVM Register Layer: UVM Register Layer, Blocks, Address maps, Register Files, Registers, Fields, DUT Integration – Register Adapter, Register Sequences, Predictor Classes.

Module 5: Reporting, UVCs: Reporting in UVM, different verbosity and log controls. Introduction to UVC. Guidelines and rules. UVC environment, UVC layering, Real time example of UVC.

Module 6: Complete UVC building: For a given Design, building an UVC – using best practices, developing fully configurable, reusable UVC and UVM Test Bench environment.

• To develop UVC and TB for a proprietary/customized/non-standard bus protocol
• Trainees have to develop the UVC using standard UVM components and develop TEST and testcases to test the UVC and its features
• Integrate DUT (supplied by trainer)  with UVC/TB and do full verification as per the vplan (supplied by trainer) and collect code coverage.