Full Time ASIC Design Verification Course starting 22nd October    Job Oriented Training    Comprehensive Placement Assistance    Full Time ASIC Design Verification Course starting 24th September    Individual Attention to each student    Max 30 Students in each batch    Full Time ASIC Design Verification Course starting 24th September    Multiple Projects and more than 60% time on Labs    Expert Trainers with strong Industry Experience
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Verification using UVM

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Verification using UVM

Verification using UVM

Course Overview:

This course is designed for working VLSI Engineers  with at least 2+ years of work experience in RTL Design / Verification / FPGA Design and has knowledge of System Verilog.

The course is designed as per the industry requirements and will be delivered by experienced engineers on Design Verification.  Importance is given to cover the concepts, methodology thoroughly with good emphasis on hands-on labs,  with 40-50% time allocated to lab sessions.

Training Delivery Model:

  • Lecture & Lab sessions go hand in hand, like corporate training.
  • Sessions will be interactive in nature.

Training Material & Certification:

  • Hand outs of training material will be provided.
  • Course completion certificate from ChipEdge.
  • Course learning will be assessed as per Bloom’s Taxonomy.
  • Certification from Global University of Engineering, USA. Very soon this may lead to giving credits leading to M.S degree.

Who Can Attend This Course:

  • Working Professionals from VLSI industry working in areas like RTL Design,Verification, FPGA Design and are interested to learn UVM & build Verification Expertise.
  • Verification / Design Engineers, who have worked or working in Verification using Verilog and used VERA / Specman ..etc in the past, But want to upgrade to latest Verification Methodologies.
  • Verification Engineers who are conversant with System Verilog, OVM / VMM methodologies and want to learn UVM
  • Faculties working in Engineering Colleges / Universities, teaching VLSI subjects like Verilog / VHDL.

Pre-requisites:

  • Hands on experience in Verification flow.
  • Good knowledge on System Verilog. If you are opting for only UVM course, Need to take online Test on System Verilog. Only qualified people are eligible to take the course.
  • Knowledge of ASIC / SOC design flow.

Course Content outline:

Each module has associated hands on labs.

Module 1: Verification Methodology, UVM Basics : Need for a Verification methodology, UVM as a template, introduction and evolution of UVM. Basic concepts of UVM.

Module 2: UVM Components- Agents, Sequencer, Sequence. Macros, TLM: Understanding UVM Test Bench – Objects, Components – Drivers, Sequencers, Sequences, Sequence item, Monitors, transactions, Introduction to Macros, Configuration Database, Resource Database. Introduction to Transaction Level modeling, Concept of TLM in UVM. TLM communications and connections – Interfaces, Ports, Exports, Imps, Analysis Ports, Building test bench for a real time design with these UVM components.

Module 3: UVM Phasing, UVM Factory and Advanced sequence control: Need for Phasing, Importance of phases and usage of phases in a typical Test Bench environment, Common Phases, Run time phases, User-Defined Phases.Introduction to Factory, Importance of dynamic binding and factory usage. Registering , creating and configuring with Examples. Handling and triggering multiple sequences and sequence body methods efficiently. Virtual Sequences

Module 4: Register Modeling using UVM Register Layer: UVM Register Layer, Blocks, Address maps, Register Files, Registers, Fields, DUT Integration – Register Adapter, Register Sequences, Predictor Classes.

Module 5: Reporting, UVCs: Reporting in UVM, different verbosity and log controls. Introduction to UVC. Guidelines and rules. UVC environment, UVC layering, Real time example of UVC.

Module 6: Complete UVC building: For a given Design, building an UVC – using best practices, developing fully configurable, reusable UVC and UVM Test Bench environment.

Project Details:

Last 2 days are dedicated exclusively for the project.

  • To develop UVC and TB for a proprietary/customized/non-standard bus protocol
  • Trainees have to develop the UVC using standard UVM components and develop TEST and testcases to test the UVC and its features
  • Integrate DUT (supplied by trainer)  with UVC/TB and do full verification as per the vplan (supplied by trainer) and collect code coverage.

Tools to be used:

  • Industry standard simulation suite
  • 24×7 lab access through VPN, to enable you spend more time on labs. This is on top of Trainer led lab sessions during sundays.

Assessment & Certification:

  • Course completion certificate from ChipEdge.
  • At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
  • Certification from Global University of Engineering, USA. Very soon this may lead to giving credits leading to M.S degree.

Trainer:

  • The trainer is working as Senior Verification Engineer with a Semiconductor Services company in Bangalore and has 19+ years of  Solid Design Verification Experience.
  • He has worked on multiple tape outs in leading semiconductor companies.
  • He is passionate about teaching and sharing his knowledge.

Lessons