Course Overview:

This course is designed for working VLSI Engineers  with at least 2+ years of work experience in RTL Design / Verification / FPGA Design and has knowledge of System Verilog.

The course is designed as per the industry requirements and will be delivered by experienced engineers on Design Verification.  Importance is given to cover the concepts, methodology thoroughly with good emphasis on hands-on labs, using cadence tools with at least 40 % time allocated to lab sessions.

Training Delivery Model:

Training Material & Certification:

• Hand outs of training material will be provided.
• Course completion certificate from ChipEdge.
• Course learning will be assessed as per Bloom’s Taxonomy.
• Certification from Global University of Engineering, USA. Very soon this may lead to giving credits leading to M.S degree.

Course Content outline:

Each module has associated hands on labs, using Cadence Incisive Simulation Tools.

Module 1: Verification Methodology, UVM Basics Need for a Verification methodology, UVM as a template, introduction and evolution of UVM. Basic concepts of UVM.

Module 2: UVM Components- agents, Sequencer, Sequence. Macros, TLM Understanding UVM Test Bench – Objects, Components – Drivers, Sequencers, Sequences, Sequence item, Monitors, transactions, Introduction to Macros, Configuration Database, Resource Database. Introduction to Transaction Level modeling, Concept of TLM in UVM. TLM communications and connections – Interfaces, Ports, Exports, Imps, Analysis Ports, Building test bench for a real time design with these UVM components.

Module 3: UVM Phasing, UVM Factory and Advanced sequence control Need for Phasing, Importance of phases and usage of phases in a typical Test Bench environment, Common Phases, Run time phases, User-Defined Phases.Introduction to Factory, Importance of dynamic binding and factory usage. Registering , creating and configuring with Examples. Handling and triggering multiple sequences and sequence body methods efficiently. Virtual Sequences

Module 4: Register Modeling using UVM Register Layer UVM Register Layer, Blocks, Address maps, Register Files, Registers, Fields, DUT Integration – Register Adapter, Register Sequences, Predictor Classes.

Module 5: Reporting, UVCs Reporting in UVM, different verbosity and log controls. Introduction to UVC. Guidelines and rules. UVC environment, UVC layering, Real time example of UVC.

Module 6: Complete UVC building For a given Design, building an UVC – using best practices, developing fully configurable, reusable UVC and UVM Test Bench environment.

Mini Project:  Last 2 days are dedicated exclusively for the project.

1. To develop UVC and TB for a proprietary/customised/non-standard bus protocol
2. Trainees have to develop the UVC using standard UVM components and develop TEST and testcases to test the UVC and its features
3. Integrate DUT (supplied by trainer)  with UVC/TB and do full verification as per the vplan (supplied by trainer) and collect code coverage.

Trainer:

• The trainer is working as Senior Verification Engineer with a Semiconductor Services company in Bangalore and has 10+ years of  Design Verification Experience.
• He has worked on multiple tape outs in leading semiconductor companies.
• He is passionate about teaching and sharing his knowledge.

Investment Amount:

It would be right investment on this high quality course, with high ROI (return on investment) considering good opportunities available for quality Verification engineers.