In today’s era, complex SoC chips are being realized using complex VLSI(EDA) tools, of which RTL2GDSII flow is being used extensively during any SoC manufacturing. This has enabled the realization of very complex digital designs, which starts with design specification and modeling of design using HDL language. This high-level description of the design is mapped to its corresponding hardware using automation, known as “Synthesis,” without which it’s near to impossible to design very complex digital circuits.
To verify the generated hardware with the original HDL description, the designer can choose functional verification using test-cases, but that is not very exhaustive. Hence there is a need for other methodology which can effectively verify the design equivalence. This is achieved by formal verification, also known as Logical Equivalence Checking (LEC).
Timing(Frequency) is one of the critical performance metrics of a Chip along with Power and Area. Timing closure is the significant milestone which dictates when a chip can be released (Tape-out) to the semiconductor foundry for fabrication. Timing Closure is a specialized skill for VLSI engineers working on RTL Design, Synthesis and Physical Design. Knowledge of Timing is also essential for most of the Engineers working on ASIC flow.
The course will be delivered by a Senior VLSI Engineer, who has worked on multiple Tape-outs for Synthesis, Timing Closure, Physical Design, and LEC. Importance is given to cover the concepts and methodology thoroughly with proper emphasis on hands-on training using Industry standard toolset, with at least 50 % of the time allocated to lab sessions.
The uniqueness of this Course:
This course offers integrated learning for Synthesis, Equivalence Checking & Sign-off STA under one umbrella using Industry Standard EDA tools. It not only covers the tool aspects but also provides in-depth technical knowledge.
What do you get out of this Course?
- In-depth know-how of using design compiler for synthesizing the design modeled in Verilog or VHDL
- Logical Equivalence check between Golden & Implemented design.
- Timing Analysis and Timing Closure of Pre-Layout(Synthesized) and Post-Layout designs.
Opportunities that could open up for you
- RTL Design/Application/CAD engineers can migrate to Synthesis/STA engineer roles or up-skill themselves to deliver effectively in their current positions.
- FPGA engineers can migrate to Synthesis/STA engineer roles.
- By acquiring Timing Closure proficiency, PD engineers can significantly improve turn around times of their blocks/designs. This, in turn, will help save valuable working hours as well as open up new growth opportunities.
Training Delivery Model:
- Weekends (Saturdays): Instructor Lead classroom training
- Weekdays: Lab support through Email and WhatsApp
- Flexible learning with 24/7 Lab Access from home through VPN
- Lecture & Lab sessions go hand in hand, like in Corporate Training Programs
- Sessions will be interactive.
- Projects at the end of the course
Who Can Attend This Course:
- M.tech (VLSI) students, who want to learn Synthesis & STA.
- RTL Design, FPGA Design, DFT as well as Physical Design engineers who want to learn Synthesis & STA thoroughly.
- Synthesis, STA Engineers who want to fill the gaps in their understanding & strengthen STA knowledge to deliver effectively in current role.
- CAD / Methodology Engineers or Application Engineers who come across Synthesis & STA in their work.
- Any working VLSI Engineer seeking to learn Synthesis & STA.
- Working knowledge of Linux.
- Knowledge of Digital Electronics Fundamentals.
- Knowledge of CMOS Fundamentals.
- Knowledge of Verilog / VHDL is a plus.
- Knowledge of ASIC / SOC design flow.
Course Content outline:
50% of the time is allocated for labs. Each lecture session will be followed by hands on lab session.
Synthesis (3 weeks):
- Introduction to Synthesis
- Synthesis Flow
- Constraining Design for timing area & power
- Understanding & Exploring .lib
- Synthesize Design
- Timing Checks
- Report, Analyze and debug results
- Optimization Techniques
- Low Power Synthesis using UPF
- Understanding the UPF and low power concepts
- Understanding of Low power cells and their requirement
- Low power synthesis using UPF file
- Scan Insertion
Formal Verification (Equivalence Check) (0.5 Weeks):
- Loading reference & implemented design
- Understanding & Matching compare points
- Verifying design & interpreting results
- Debugging Verification
Static Timing Analysis (3.5 weeks):
- STA overview & concepts
- Clocking – Handling clock muxes, clock dividers
- Generated clocks, Clocking Exceptions
- Timing Exceptions
- Post Layout STA using SPEF
- Multi-Mode, Multi-Corner STA
- Derates, OCV, Variations – Source and cause
- Crosstalk & Noise Analysis
- Timing ECOs generation, What-If Analysis
- Timing Challenges
Tools to be used:
- Synopsys ( Design Compiler & Prime Time )
- Additional Lab Hours through VPN, to enable you to spend more time on labs from home. This is on top of Trainer led lab sessions on weekends.
Assessment & Certification:
- Course completion certificate from ChipEdge.
- At the end of the course, Course learning is assessed as per Bloom’s Taxonomy.
The Trainer has started his career with ST Micro and subsequently worked with Virage Logic, LSI. Currently, he is working with a leading product Semiconductor Company (MNC), handling Sign-off STA and PD.
He has a total of 13+ years of industry experience. He has worked on multiple tape outs, with working Silicon.
His area of Expertise includes Sign-off Timing Analysis and Physical Design. And has good hands on experience on RTL to GDSII flow, starting from RTL design to Synthesis, DFT.
He has published technical papers and presented in the industry conferences. He is passionate about teaching and sharing his knowledge.