Overview:

In today’s era, complex SoC chips are being realized using complex VLSI(EDA) tools, of which RTL2GDSII flow is being used extensively. This has enabled the realization of very complex digital designs, which starts with modeling of design using HDL language. This high-level description of the design is mapped to its corresponding hardware using automation, known as “Synthesis,” without which it’s near to impossible to design very complex digital circuits.

To verify the generated hardware with the original HDL description, the designer can choose functional verification using test-cases, but that is not very exhaustive and time consuming. Hence there is a need for other methodology which can effectively verify the design equivalence. This is achieved with Logical Equivalence Checking (LEC).

Timing(Frequency) is one of the critical performance metrics of a Chip along with Power and Area. Timing closure is the significant milestone which dictates when a chip can be released (Tape-out) to the semiconductor foundry for fabrication. Timing Closure is a specialized skill for VLSI engineers working on RTL Design, Synthesis and Physical Design. Knowledge of Timing is also essential for most of the Engineers working on ASIC flow.

Training Delivery Model:
  • Instructor-Led Online Live Virtual classroom training
  • Timings : 9:30 am to 1 pm (saturday & sunday)

          Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

  • Module specific Lecture sessions and Labs conducted hand-in-hand
  • Emphasis on Lab driven hands-on training aimed at building key skills
  • Weekdays: Lab support through Email and WhatsApp
  • Flexible learning with Lab Access from home through VPN
Training Materials:
  • Soft copies of training materials will be provided, through LMS (online learning management system) which can be accessed online any time, any device.
The uniqueness of this Course:

This course offers integrated learning for Synthesis, Equivalence Checking & Sign-off STA under one umbrella using Synopsys tools, who is leader in this space. It not only covers concepts, the tool aspects but also provides in-depth technical knowledge.

What do you get out of this Course?
  • In-depth know-how of using design compiler for synthesizing the design modeled in Verilog or VHDL
  • Logical Equivalence check between Golden & Implemented design.
  • Timing Analysis and Timing Closure of Pre-Layout(Synthesized) and Post-Layout designs.
How this Course Can help you
  • RTL Design/Application/CAD engineers can migrate to Synthesis/STA engineer roles or up-skill themselves to deliver effectively in their current positions.
  • FPGA engineers can migrate to Synthesis/STA engineer roles.
  • By acquiring Timing Closure proficiency, PD engineers can significantly improve turn around times of their blocks/designs. This, in turn, will help save valuable working hours as well as open up new growth opportunities.
Certification:

Course completion certificate will be provided, for all eligible candidates who meets the course completion criteria. The assessment process include evaluating the assignments and final written test.

Placement Assistance
  • Placement assistance is not available for online courses. These are skill development courses only to upskill yourself. If you are looking for job, you need to help yourself.

Who Can Attend This Course:
  • M.tech (VLSI) students, who want to learn Synthesis & STA.
  • RTL Design, FPGA Design, DFT as well as Physical Design engineers who want to learn Synthesis & STA thoroughly.
  • Synthesis, STA Engineers who want to fill the gaps in their understanding & strengthen STA knowledge to deliver effectively in current role.
  • CAD / Methodology Engineers or Application Engineers who come across Synthesis &  STA in their work.
  • Any working VLSI Engineer seeking to learn Synthesis & STA.

Pre-requisites:

  • Working knowledge of Linux.
  • Knowledge of Digital Electronics Fundamentals.
  • Knowledge of CMOS Fundamentals.
  • Knowledge of Verilog.
  • Knowledge of ASIC / SOC design flow.

 

Course Content outline:

50% of the time is allocated for labs. Each lecture session will be followed by hands on lab session.

Synthesis (3.5 weeks):

  • Introduction to Synthesis
  • Synthesis Flow
  • Constraining Design for timing area & power
  • Understanding & Exploring .lib
  • Synthesize Design
  • Timing Checks
  • Report, Analyze and debug results
  • Optimization Techniques
  • Low Power Synthesis using UPF
    • Understanding the UPF and low power concepts
    • Understanding of Low power cells and their requirement
    • Low power synthesis using UPF file
  • Scan Insertion

Formal Verification (Equivalence Check) (0.5 Weeks):

  • Loading reference & implemented design
  • Understanding & Matching compare points
  • Verifying design & interpreting results
  • Debugging Verification

Static Timing Analysis (4 weeks):

  • STA overview & concepts
  • Clocking – Handling clock muxes, clock dividers
  • Generated clocks, Clocking Exceptions
  • Timing Exceptions
  • Post Layout STA using SPEF
  • Multi-Mode, Multi-Corner STA
  • Derates, OCV, Variations – Source and cause
  • Crosstalk & Noise Analysis
  • Timing ECOs generation, What-If Analysis
  • Timing Challenges

Synopsys Tools to be used:
  • Synthesis – Design Compiler Topographical
  • LEC : Formality
  • Static Timing Analysis(STA): Prime Time SI
Lab Access:
  • Lab Access will be provided through VPN.
  • Weekly 14 hours of Lab access is provided.
  • Can be accessed in 24×7 mode.
  • Can use, allocated usage limit anytime within the week.
Extra Lab Hours Per Week
  • If you need more than 14 hours of lab access per week, it is possible to provide at extra cost.
  • please get in touch with our course counselors, through enquiry forms.

Trainer:

The trainer has a total of 20+ years of industry experience at Texas Instruments and Wipro working on multiple tape outs.

The area of  Expertise includes Sign-off Timing Analysis with experience on complete RTL to GDSII flow, starting from RTL design, Synthesis, DFT and Physical Design.

The trainer has published technical papers and is a patent holder who is passionate about teaching and sharing knowledge.

Course Fee:
  • Rs 30,000  without VPN extension after last day of course work.
  • Rs 34,000 with VPN extension of 2 weeks  after last day of course work.
  • 18% GST will be applicable.
Payment Options:
  • We accept all Credit / debit cards.
  • We do not accept any cash payments.
Lab Access:
  • Weekly 14 hours of Lab access is provided.
Extra Lab Hours Per Week
  • If you need more than 14 hours of lab access per week like 20 / 30 / 40 hrs, it is possible to provide at extra cost.
  • For getting customized lab access, please get in touch with our course counselors, through enquiry forms.

TESTIMONIALS

Enquire Now
  • 8 Weeks (ADMISSION CLOSED)DURATION:
  • 28th March 2020 STARTS FROM:

Recent Posts

Setup Menus in Admin Panel

X