Career growth for a DFT Engineer DFT or “Design For Testability” is a...
This VLSI course comprehensively convers the synthesis, static timing analysis and LEC, along with hands on labs using Design Compiler, Prime Time and Formality.
Training Delivery Model
- Instructor-Led Live Online Training
- Timings: 9:30 am to 1 pm (Saturday & Sunday)
- Module-specific Lecture sessions and Labs conducted hand-in-hand
- Emphasis on Lab driven hands-on training aimed at building key skills
- Weekdays: Lab support through Email and WhatsApp
- Flexible learning with Remote Lab Access through VPN
- In-depth know-how of using design compiler for synthesizing the design modeled in Verilog or System Verilog.
- Logical Equivalence Checking between Golden & Implemented design.
- Timing Analysis and Timing Closure of Pre-Layout(Synthesized) and Post-Layout designs.
How this Course Help in Your Career Growth
- RTL Design/Application/CAD engineers can migrate to Synthesis/STA engineer roles or up-skill themselves to deliver effectively in their current positions.
- FPGA engineers can migrate to Synthesis/STA engineer roles.
- By acquiring Timing Closure proficiency, PD engineers can significantly improve turn around times of their blocks/designs. This, in turn, will help save valuable working hours as well as open up new growth opportunities.