Career growth for a DFT Engineer DFT or “Design For Testability” is a...
The Synthesis and STA course In today’s era, complex SoC chips are being realized using complex VLSI(EDA) tools, of which RTL2GDSII flow is being used extensively. This has enabled the realization of very complex digital designs, which start with modeling of design using HDL language. This high-level description of the design is mapped to its corresponding hardware using automation, known as “Synthesis,” without which it’s near to impossible to design very complex digital circuits.
To verify the generated hardware with the original HDL description, the designer can choose functional verification using test-cases, but that is not very exhaustive and time-consuming. Hence there is a need for other methodology which can effectively verify the design equivalence. This is achieved with Logical Equivalence Checking (LEC).
Timing(Frequency) is one of the critical performance metrics of a Chip along with Power and Area. Timing closure is the significant milestone that dictates when a chip can be released (Tape-out) to the semiconductor foundry for fabrication. Timing Closure is a specialized skill for VLSI engineers working on RTL Design, Synthesis and Physical Design. Knowledge of Timing is also essential for most of the Engineers working on ASIC flow.
Training Delivery Model
- Instructor-Led Online Live Virtual classroom training
- Timings: 9:30 am to 1 pm (Saturday & Sunday)
- Module-specific Lecture sessions and Labs conducted hand-in-hand
- Emphasis on Lab driven hands-on training aimed at building key skills
- Weekdays: Lab support through Email and WhatsApp
- Flexible learning with Lab Access from home through VPN
- Soft copies of training materials will be provided, through LMS (online learning management system) which can be accessed online at any time, any device.
The uniqueness of this Course
This synthesis and sta course offer integrated learning for Synthesis, Equivalence Checking & Sign-off STA under one umbrella using Synopsys tools, who is a leader in this space. It not only covers concepts, the tool aspects but also provides in-depth technical knowledge.
What do you get out of this Course?
- In-depth know-how of using design compiler for synthesizing the design modeled in Verilog or VHDL
- Logical Equivalence check between Golden & Implemented design.
- Timing Analysis and Timing Closure of Pre-Layout(Synthesized) and Post-Layout designs.
How this Course Can help you
- RTL Design/Application/CAD engineers can migrate to Synthesis/STA engineer roles or up-skill themselves to deliver effectively in their current positions.
- FPGA engineers can migrate to Synthesis/STA engineer roles.
- By acquiring Timing Closure proficiency, PD engineers can significantly improve turn around times of their blocks/designs. This, in turn, will help save valuable working hours as well as open up new growth opportunities.
STA course completion certificate will be provided, for all eligible candidates who meet the course completion criteria. The assessment process includes evaluating the assignments and final written test.