Course Overview 

This VLSI course comprehensively convers the synthesis, static timing analysis and LEC, along with hands on labs using Design Compiler, Prime Time and Formality.

Training Delivery Model

  • Instructor-Led Live Online Training
  • Timings9:30 am to 1 pm (Saturday & Sunday)
  • Module-specific Lecture sessions and Labs conducted hand-in-hand
  • Emphasis on Lab driven hands-on training aimed at building key skills
  • Weekdays: Lab support through Email and WhatsApp
  • Flexible learning with Remote Lab Access through VPN

Learning Outcomes

  • In-depth know-how of using design compiler for synthesizing the design modeled in Verilog or System Verilog.
  • Logical Equivalence Checking  between Golden & Implemented design.
  • Timing Analysis and Timing Closure of Pre-Layout(Synthesized) and Post-Layout designs.

How this Course Help in Your Career Growth

  • RTL Design/Application/CAD engineers can migrate to Synthesis/STA engineer roles or up-skill themselves to deliver effectively in their current positions.
  • FPGA engineers can migrate to Synthesis/STA engineer roles.
  • By acquiring Timing Closure proficiency, PD engineers can significantly improve turn around times of their blocks/designs. This, in turn, will help save valuable working hours as well as open up new growth opportunities.

Who Can Benefit From This Course

  • M.tech (VLSI) Interns/students, who want to learn Synthesis and Static Timing Analysis.
  • RTL Design, FPGA Design, DFT as well as Physical Design engineers who want to learn Synthesis and STA course thoroughly.
  • Synthesis, STA Engineers who want to fill the gaps in their understanding & strengthen STA knowledge to deliver effectively in the current role.
  • CAD / Methodology Engineers or Application Engineers who come across Synthesis and  STA in their work.
  • Any working VLSI Engineer seeking to learn Synthesis and STA.

Pre-requisites

  • Working knowledge of Linux.
  • Knowledge of Digital Electronics Fundamentals.
  • Knowledge of CMOS Fundamentals.
  • Knowledge of Verilog.
  • Knowledge of ASIC / SOC design flow.

Tools To Be Used

  • Synthesis: Design Compiler
  • Static Timing Analysis: Prime Time SI
  • LEC:  Formality

Lab Access

  • Lab Access will be provided through a VPN.
  • Weekly 14 hours of Lab access is provided.
  • Can be accessed in 24×7 mode.
  • Can use, allocated usage limit anytime within the week.

Extra Lab Hours Per Week or After the Course

  • If you need more than 14 hours of lab access per week or after the course as per your learning need, it is possible to provide at extra cost.
  • please get in touch with our Learning Advisor.

Curriculum

Synthesis
  • Introduction to Synthesis
  • Synthesis Flow
  • Constraining Design for timing area & power
  • Understanding & Exploring .lib
  • Synthesize Design
  • Timing Checks
  • Report, Analyze and debug results
  • Optimization Techniques
  • Low Power Synthesis using UPF
    • Understanding the UPF and low power concepts
    • Understanding of Low power cells and their requirement
    • Low power synthesis using UPF file
  • Scan Insertion
Static Timing Analysis (STA)
  • STA overview & concepts
  • Clocking – Handling clock muxes, clock dividers
  • Generated clocks, Clocking Exceptions
  • Timing Exceptions
  • Post Layout STA using SPEF
  • Multi-Mode, Multi-Corner STA
  • Derates, OCV, Variations – Source and cause
  • Crosstalk & Noise Analysis
  • Timing ECOs generation, What-If Analysis
  • Timing Challenges
Equivalence Checking
  • Loading reference & implemented design
  • Understanding & Matching compare points
  • Verifying design & interpreting results
  • Debugging the Non Equivalents

Trainer

The trainer has a total of 20+ years of industry experience at Texas Instruments and Wipro working on multiple tape-outs.

The area of  Expertise includes Sign-off Timing Analysis with experience on complete RTL to GDSII flow, starting from RTL design, Synthesis, DFT, and Physical Design.

The trainer has published technical papers and is a patent holder who is passionate about teaching and sharing knowledge.

 

Fees

₹ 30,000

Regular Price     ₹ 40,000       + 18% of GST

₹30,000  without Lab extension after the last day of course work.

₹34,000 with Lab extension of 2 weeks after the last day of course work.

No Cost EMI Option Available

Pay in Easy Installments at no extra cost

We accept all Credit/debit cards/net banking/UPI payment Options

Placement Assistance

Placement Assistance is provided to the interested candidates, by arranging interview opportunities with the hiring companies.

Know more where our students and got a job so far

 

100% Money-Back Guarantee

ChipEdge believes in quality and professional approach in what we offer, which earned a reputation from industry & professionals.

Please visit refund policy for more details 

Demo video

A small clip from the recent online lecture session

Lab Session

A small clip from the recent online lab session

Trainee Reviews

Frequently asked questions (FAQS)

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves. 

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences  is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Design Compiler, Prime Time & Formality, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It depends on the course package you choose, as per your learning need. For basic package, no extension of lab access. You can choose the either 2 weeks extension course package or choose custom duration like 1 month with your desired number of hours per week.

Please speak to our Learning Advisor for further details.

We do have part payment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs.  please check with our Learning Advisor.

Course completion certificates will be provided, whoever meets the course completion criteria.

Placement Assistance is provided to the interested candidates. Typically majority of the candidates join our courses to enhance to their skills and help themselves in job change.

Enquire Now
  • 8 Weeks DURATION:
  • October 17, 2020STARTS FROM:

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