In todays era complex SoC chips are being realized using CAD automations, of which RTL2GDSII flow is being used extensively during any SoC manufacturing. This has enabled to realize very complex digital design, which starts with the design specification and modeling of design using HDL language. This high level description of design is mapped to its corresponding hardware using automation, known as “Synthesis”, without which it’s near to impossible to design very complex digital circuit. Also, in order to verify that generated hardware with the original HDL description, designer either can choose functional verification using test-cases, but that is not very exhaustive. Hence there is need of other methodology which can effectively verify the design equivalence. This is achieved by formal verification (also know as logical equivalence checking, in short LEC).
Timing is one of the key performance metric of a Chip other than Power, Area and Timing closure is the major milestone which dictates when a chip can be released (tape out) to the semiconductor foundry for fabrication. Timing Closure is important Skill for a VLSI engineer and knowledge of Timing is essential for most of the Engineers working on ASIC flow. This course is designed for the working VLSI engineers who want to learn / enhance their knowledge on Static Timing Analysis (STA).
The course will be delivered by a Senior VLSI Engineer, who has worked on multiple tape outs for Synthesis, timing closure, Physical Design, LEC. Importance is given to cover the concepts, methodology thoroughly with good emphasis on hands-on training, using Industry standard tool set, with at least 50 % time allocated to lab sessions.
Uniqueness of this Course:
This course offers integrated learning for synthesis, equivalence checking & sign-off STA under one umbrella with exposure Industry standard EDA tools. It’s not only covered the tool aspect but also provides in depth technical knowledge.
What do you get out of this Course?
Synthesis sign-off STA course offers in depth know-how of using design compiler for synthesizing the design modelled in Verilog or VHDL. It also offers the logical equivalence check between the golden & implemented design along-with the timing analysis of synthesized design. It provides the opportunity to learn the synthesis, LEC & timing analysis which is imperative to get the silicon working first hand for the very complex design.
What Opportunities could open up for you?
Having been exposed the to the synthesis, equivalence checking & timing analysis, a participant is well poised to expand its horizon of technical skills which, in turn, assist achieving growth vertically up in technical pyramid, whether he is RTL designer, a verification engineer, PCB design engineer, FPGA engineer or physical implementation engineer (PnR). Having expertise in all aspect of RTL2GDSII flow, particularly synthesis sign-off sta, shall enable you to lead the chip design qualitatively. Also, todays semiconductor industry demands integrated expertise, either as RTL designer, synthesis & STA or synthesis, STA and PnR.
Training Delivery Model:
- Weekends (Saturdays) : Instructor Lead classroom training
- Weekdays : Lab support through Email and WhatsApp
- Flexible learning with 24/7 Lab Access from home through VPN
- Lecture & Lab sessions go hand in hand, like corporate training
- Sessions will be interactive in nature
- Projects at end of the course
Who Can Attend This Course:
- Working Professionals from VLSI industry, currently working in some area (RTL Design,Verification, FPGA Design, DFT, Physical design, low power..) who want to learn Synthesis & STA thoroughly.
- Synthesis, STA Engineers who want to fill the gaps in their understanding & strengthen STA knowledge to deliver effectively in current role.
- CAD / Methodology Engineers or Application Engineers who come across Synthesis & STA in their work, but doesn’t have good understanding.
- Any working VLSI Engineer seeking to learn Synthesis & STA.
- Faculties working in Engineering Colleges / Universities, teaching VLSI subjects.
- M.tech (VLSI) students, who want to learn Synthesis & STA.
- Working knowledge of linux.
- Knowledge of digital Electronics fundamentals.
- Knowledge of CMOS fundamentals.
- Knowledge of Verilog / VHDL is a plus
- Knowledge of ASIC / SOC design flow
Course Content outline:
50% of the time is allocated for labs. Each lecture session will be followed by hands on lab session.
Synthesis (3 weeks) :
- Introduction to Synthesis
- Synthesis Flow
- Constraining Design for timing area & power
- Understanding & Exploring .lib
- Synthesize Design
- Timing Checks
- Report, Analyze and debug results
- Optimization Techniques
- Low Power Synthesis using UPF
Understanding the UPF and low power concepts
Understanding of Low power cells and their requirement
Low power synthesis using UPF file
- Scan Insertion
Formal Verification (Equivalence Check) (0.5 Weeks)
- Loading reference & implemented design
- Understanding & Matching compare points
- Verifying design & interpreting results
- Debugging Verification
Static Timing Analysis (3.5 weeks) :
- STA overview & concepts
- Clocking – Handling clock muxes, clock dividers
- Generated clocks, Clocking Exceptions
- Timing Exceptions
- Post Layout STA using SPEF
- Multi Mode, Multi Corner STA
- Derates, OCV, Variations – Source and cause
- Crosstalk & Noise Analysis
- Timing ECOs generation, What-If Analysis
- Timing Challenges
Tools to be used:
- Industry Standard Tools
- Additional Lab Hours through VPN, to enable you spend more time on labs from home. This is on top of Trainer led lab sessions on weekends.
Assessment & Certification:
- Course completion certificate from ChipEdge.
- At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
- Certification and Course Credits leading to M.S. degree, from Global University of Engineering, USA
The Trainer has started his career with ST Micro and sebsequently worked with Virage Logic, LSI. Currently he is working with a leading product Semiconductor Company (MNC) , handling Sign-off STA and PD.
He has a total of 13+ years of industry experience. He has worked on multiple tape outs, with working Silicon.
His area of Expertise includes Sign-off Timing Analysis and Physical Design. And has good hands on experience on RTL to GDSII flow, starting from RTL design to Synthesis, DFT.
He has published technical papers and presented in the industry conferences. He is passionate about teaching and sharing his knowledge.
My expectation was to get thorough knowledge of STA. After joining this course things are more clear now and some exposure of LEC. Trainer is having good knowledge of STA concepts. and the supporting examples are also good and related to real scenarios so we can relate it to design. VPN facility was good. It is very user friendly facility that enables us to access tools easily. Overall program was good. It helped me to explore my knowledge.
I have joined this course to gain good practical knowledge on STA and synthesis, by using PT & DC tools. Trainer has very strong technical expertise & course has met all my expectations. Now I am confident enough, to handle some complex STA in day to day work. I could spend extra time on Labs & assignments, because of VPN facility.
It was a great experience with the trainer of good expertise & patience. The course has given me enough exposure and hands-on, on prime time tool and real time scenarios. VPN facility is really unique & helps us for self learning, when compared to other training institutes. I would like to attend the further courses in future.
Clearing all the doubts with the help of circuit diagrams and use cases,has helped very much in understanding. Course gave me,good exposure to STA. VPN facility has really helped to continue the learning in weekdays.
The Trainer is really good and helps one to understand the concepts right from the basics. Lab sessions, assignments and projects are very helpful for practical understanding. Now, I am confident enough in handling the timing issues.