This course covers the different aspects of scan chain insertion, which includes Introduction to DFT & SCAN, Scan Architectures, DFT DRC rule checks, analyze & fix the DRC violations, configure the scan chains as per the scan architecture of chip, in terms of number of scan chains, scan chain length, pin sharing, integrating IPs into scan chains, scan compression, address the coverage goals and export the files to ATPG tools.
Objectives / Outcome:
At the end of the course the candidate will be able to:
- Specify the scan testing architecture.
- Debug & fix DFT DRC violations.
- Configure & Insert Scan chains.
- Insert scan compression with OCC-based configuration,
- Handle black-box modules such as memories & analog units.
- Boundary scan insertion
- Create scandef & test protocol files & hand-off the scan-inserted netlist to ATPG & Physical Design teams.
Training Delivery Model:
- Lecture & Lab sessions go hand in hand, like corporate training.
- Sessions will be interactive in nature.
Who Can Attend This Course:
- Entry level / Experienced DFT engineers, who want to learn Scan Insertion / DFT in a systematic way from fundamentals to techniques, Methodologies.
- RTL Design, Verification, Synthesis, STA and Physical Design Engineers, CAD Engineers who need to understand DFT for effective integration into their respective design flows.
- Application Engineers who need to understand DFT, for effective customer interactions & problem solving
- Faculty working in Engineering Colleges, teaching VLSI subjects.
- Anyone interested to learn basic to intermediate level of DFT concepts and tool flow.
- M.tech (VLSI) students.
- Knowledge of digital design.
- Knowledge of ASIC / SOC design flow.
- At least 1 year of work experience in ASIC or SOC Design Flow.
- Prior knowledge of DFT is not required
Course Content outline:
Each lecture session will be followed by lab sessions on that topic.
- Full ASIC flow – DFT
- DFT Basics
- Understanding of SCAN in depth
- Scan architecture overview
- Types of Scan
- Scan golden rules
- Understanding and analysis of DFT DRC
- Multiple clock handling
- DRC Fixing with examples
- Full scan insertion and stitching without compression
- Generate test protocol and understanding
- Basics/Need of Compression
- Compression techniques
- Scan insertion with compression
- On-chip clocking for at-speed testing
- Hierarchical Scan Design
- Top-Down Scan Insertion
- Boundary scan basics
- Boundary scan cell operation in detail
- JTAG basics, operation and state machine
Tools to be used:
- Industry Standard DFT Tool set will be used.
- Additional Lab Hours through VPN, to enable you spend more time on labs from home. This is on top of Trainer led lab sessions during Saturdays.
Assessment & Certification:
- Course completion certificate from ChipEdge.
- At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
- Certification from Global University of Engineering, USA.
The trainer is really good and has strong knowledge and expertise in DFT. Labs are designed very well, adequate with the course requirements.
The trainer is good and has put his efforts to prepare the content and delivered the course very well.
The course was really good and able to learn tool oriented way. Trainer was really good and he explained each and every topic. He was able to clear all our doubts. He is having a very good knowledge in the DFT domain and expertise in tools. Met most of my Expectation.
Concepts were explained with focus on Fundamentals. Labs are very well formulated making us understand the significance of each step and command. Trainer has a very good expertise in DFT along with the patience to deliver it to the students, reaching to their level of understanding. Gives personal attention to everyone in the class. VPN has helped to work at home and get good hands on.
Labs were very helpful and it helped me understand scan concepts very well. Trainer was very knowledgeable and helped us in understanding concepts. It bridged gap between industry and academics.