The course is designed and will be delivered by experts in physical design, as per the industry requirements. Importance is given to cover the concepts, methodology with good emphasis on hands-on training, using Industry Standard tools with at least 60 % time allocated to lab sessions with the quality project at the end of the course.

Training Delivery Model:
  • Instructor-Led Online Live Virtual classroom training
  • Timings : 9:30 am to 1 pm (saturday & sunday)

          Session Details:

          9.30 am to 11.00 am – Lecture session

          11.00 am to 11.30 am – Tea Break

          11.30 am to 01.00 pm – Lab Session

  • Module specific Lecture sessions and Labs conducted hand-in-hand
  • Emphasis on Lab driven hands-on training aimed at building key skills
  • Weekdays: Lab support through Email and WhatsApp
  • Flexible learning with Lab Access from home through VPN
Training Materials:

Soft copies of training materials will be provided, through LMS (online learning management system) which can be accessed online any time, any device.


Course completion certificate will be provided, for all eligible candidates who meets the course completion criteria. The assessment process include evaluating the assignments and final written test.

Placement Assistance 

Placement assistance is not available for online courses.These are the skills development course only to upskill yourself.if you are looking for job,you need to help yourself.


Who Can Attend This Course?
  • B.Tech or M.Tech Freshers/Students/Interns looking to start a career in VLSI.
  • Working Professionals from VLSI industry, currently working in some area (RTL Design, Verification, FPGA Design, Analog Layout, Synthesis, STA, Characterisation, Board Level Testing, etc.), but want to switch to Physical design (PD).
  • Working Physical Design Engineers who want to fill the gaps in their understanding & strengthen Physical Design knowledge to deliver effectively in their current role.
  • Working Professionals in Embedded / Electronics (PCB designing, assembling, testing..) and interested in changing Career into VLSI industry.
  • Faculty working in Engineering Colleges / Universities, teaching VLSI subjects.
Educational Qualifications
  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S  in VLSI / Embedded Systems / Electronics / Similar



Knowledge on below topics is Required.

  1. Working knowledge of Linux.
  2. Knowledge of digital Electronics Fundamentals.
  3. Knowledge of CMOS Fundamentals.
  4. Knowledge of Verilog / VHDL is a plus
  5. Knowledge of ASIC / SOC design flow is a plus


Course Outline:

Module 1: CMOS fundamentals & Introduction to Physical Design

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 2: Inputs & Sanity Check

List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD flow, contents of each input, qualifying the received inputs and sanity checks.

Module 3: Floorplan

Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines.

Module 4: Power Routing:

Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail.

Module 5: Placement

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis,Scan chain re-order, Regioning/Grouping/Bounds.

Module 6: Timing Analysis & Optimization

Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same.

Module 7: Clock Tree Synthesis (CTS)

Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.

Module 8: Routing

Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum routing results.

Module 9: ECO Flow

What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing.

Module 10: Sign-off Checks

Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.

Module 11: Project

One projects will be given covering Netlist to GDS flow. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to complete routing, after cleaning all the issues during sign-off checks.

Tools to be used:
  • ChipEdge uses latest versions of below synopsys tools for different modules of the course. Each Student gets dedicated license for full day.
  • Physical Design:  IC Compiler 2 (ICC2)
  • RC Extraction: Star RC
  • Physical Verification: IC Validator
  • Static Timing Analysis(STA): Prime Time SI
  • Synopsys ICC2 is a leader in Physical Design tools and used by the majority of the MNCs/ product companies in Bangalore / India
Lab Access:
  • Lab Access will be provided through VPN.
  • Weekly 14 hours of Lab access is provided.
  • Can be accessed in 24×7 mode.
  • Can use, allocated usage limit anytime within the week.
Extra Lab Hours Per Week
  • If you need more than 14 hours of lab access per week, it is possible to provide at extra cost.
  • please get in touch with our course counselors, through enquiry forms.


The trainer is working as Lead Physical Design Engineer with a leading VLSI Company in Bangalore and has 11+ years of Physical Design experience in VLSI industry, with multiple complex tape outs to his credit.

He is passionate about teaching and mentored many entry / mid-level engineers throughout his corporate career. He is an excellent Trainer and has received excellent credentials for all his training deliveries. He is dynamic and brings high energy levels to the class.

He teaches from his rich industry experience, with case studies of various design problems he has faced while working as PD Engineer.

Course Fee:
  • Rs 40,000  without VPN extension after last day of course work.
  • Rs 44,000  with VPN extension of 2 weeks after last day of course work.
  • 18% GST will be applicable.
Payment Options:
  • We accept all Credit / debit cards.
  • We do not accept any cash payments.
Lab Access:
  • Weekly 14 hours of Lab access is provided.
Extra Lab Hours Per Week
  • If you need more than 14 hours of lab access per week like 20 / 30 / 40 hrs, it is possible to provide at extra cost.
  • For getting customized lab access, please get in touch with our course counselors, through enquiry forms.


Enquire Now
  • 12 weeksDURATION:
  • 18thJuly 2020 STARTS FROM:

Class Timings

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