Comprehensive Learning
Duration & Timing for Optimal Learning:
Prerequisite: CMOS fundamentals & Introduction to Physical Design
Module 1: Synthesis
Module 2: Inputs & Sanity Check
Module 3: Floorplan
Module 4: Power Routing:
Module 5: Placement
Module 6: Timing Analysis & Optimization
Module 7: Clock Tree Synthesis (CTS)
Module 8: Routing
Module 9: ECO Flow
Module 10: Sign-off Checks
Module 11: TCL Scripting
Module 12: Projects
Topic: The Role of DFT Engineer in SOC Design & Career Opportunities
Speaker: Mittu George P, DFT Engineer, Celton Semiconductors Pvt Ltd
Date: March 16, 2024, at 10:00 AM IST