Course Overview

Physical Design in VLSI Design cycle involves preparing the design for fabrication at a selected foundry (TSMC, Global foundries ..), with a specific technology node (10nm, 7nm..). This process involves several steps starting with floor planning and ending with delivering GDS2 files to foundry after doing all sign off checks.

Physical Design has evolved as complex specialization and in demand skill for last 2 decades.  This course will give decent exposure on physical design concepts, techniques, along with hands on labs and a project at the end.

Training Delivery Model

  • Instructor-Led Online Live Training
  • Timings9:30 am to 1 pm (Saturday & Sunday)
  • Module-specific Lecture sessions and Labs conducted hand-in-hand
  • Emphasis on Lab driven hands-on training aimed at building key skills
  • Weekdays: Lab support through WhatsApp
  • Flexible learning with Lab Access from home through VPN

Training Materials

Soft copies of training materials will be provided, through LMS (online learning management system) which can be accessed online at any time, any device.

Certification

Course completion certificate will be provided who meet the course completion criteria. The assessment process includes evaluating the assignments and final written test.

Who Can Attend This Course?

  • B.Tech/M.Tech freshers who have done Internships with any VLSI companies and are interested to improve skills.
  • Working Professionals from the VLSI industry, currently working in some areas (RTL Design, Verification, FPGA Design, Analog Layout, Synthesis, STA, Characterization), but want to switch to Physical design (PD).
  • Working Physical Design Engineers who want to fill the gaps in their understanding & strengthen Physical Design knowledge to deliver effectively in their current role.
  • Working Professionals in Embedded / Electronics (PCB designing, assembling, testing..) and interested in changing Career into the VLSI industry.
  • Faculty working in Engineering Colleges / Universities, teaching VLSI subjects.

Educational Qualifications

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S  in VLSI / Embedded Systems / Electronics / Similar

Pre-Requisites

Knowledge of the below topics is Required.

  1. Working knowledge of Linux.
  2. Knowledge of digital Electronics Fundamentals.
  3. Knowledge of CMOS Fundamentals.
  4. Knowledge of Verilog / VHDL is a plus
  5. Knowledge of ASIC / SOC design flow is a plus

Course Outline

Module 1: CMOS fundamentals & Introduction to Physical Design

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 2: Inputs & Sanity Check

List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD flow, contents of each input, qualifying the received inputs and sanity checks.

Module 3: Floorplan

Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 4: Power Routing:

Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 5: Placement

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Regioning/Grouping/Bounds.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 6: Timing Analysis & Optimization

Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 7: Clock Tree Synthesis (CTS)

Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 8: Routing

Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum routing results.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 9: ECO Flow

What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 10: Sign-off Checks

Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Module 11: Project

One projects will be given covering Netlist to GDS flow. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to complete routing, after cleaning all the issues during sign-off checks.

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design flow.

Tools to be used

  • ChipEdge uses the latest versions of Synopsys tools for different modules of the course. Each Student gets dedicated license for a full day.
  • Physical Design:  IC Compiler 2 (ICC2)
  • RC Extraction: Star RC
  • Physical Verification: IC Validator
  • Static Timing Analysis(STA): Prime Time SI
  • Synopsys ICC2 is a leader in Physical Design tools and used by the majority of the MNCs/ product companies in Bangalore / India

Lab Access

  • Lab Access will be provided through a VPN.
  • Weekly 14 hours of Lab access is provided.
  • It can be accessed in 24×7 mode.
  • Can use, allocated usage limit anytime within the week.

Extra Lab Hours Per Week

  • If you need more than 14 hours of lab access per week, it is possible to provide at extra cost.
  • please get in touch with our course counselors, through enquiry forms.

 

Course Fee

Actual Price 

₹ 60,000

Rs 40,000  without Lab extension after the last day of course work.

Rs 44,000  with Lab extension of 2 weeks after the last day of course work.

18% of GST will be applicable.

No Cost EMI Option Available

Pay in Easy Installments at no extra cost, through our partners. please speak to our Learning Advisor for details.

Payment Options

We accept Credit/debit cards / UPI / Net banking payment options.

Placement Assistance

Typically these online courses are skill improvement courses. Job Assistance is provided to the interested candidates. Please speak to our Learning Advisor for further details.

Trainer

The trainer is working as Lead Physical Design Engineer with a leading VLSI Company in Bangalore and has 11+ years of Physical Design experience in VLSI industry, with multiple complex tape outs to his credit.

He is passionate about teaching and mentored many entry / mid-level engineers throughout his corporate career. He is an excellent Trainer and has received excellent credentials for all his training deliveries. He is dynamic and brings high energy levels to the class.

He teaches from his rich industry experience, with case studies of various design problems he has faced while working as PD Engineer.

Lecture Demo video

A small clip from the recent online lecture session

Lab Demo Video

A small clip from the recent lab session

Traine Reviews

Reviews

I joined this course to get enough confidence in PD so that I can switch my profile from IT to PD. The complete course package is good. Facilities are as expected. A trainer is a person who doesn’t show off his experience and treat everyone as equal. I haven’t heard the trainer is saying “Don’t Know” for any of the questions raised from our end. The quality-wise trainer shares his expertise without any hesitation. No issues found with the co-ordination. Teams considered my long travel and have kept me aware of any schedule changes considering my long travel as I use to travel from Chennai on every weekend to attend this course.

Surender, PD Engineer, IBM

My expectations to join this course was to understand complete PD flow, practically implementing
the theoretical knowledge of PD and taking the design from RTL to GDSII. The trainer knows in and out
of the PD. I just say that I am lucky to get trained by him. The trainer gave equal opportunity to everyone
to resolve doubts faced by candidates. Overall, I am satisfied with the course and it met my
expectations.

Sadiq, PD Engineer, Global Foundries

As a fresher, I wanted to gain knowledge in physical design. The trainer has explained the complete flow very nicely. The complete flow was explained which was needed to crack the interview. Concepts were very clearly explained in class. The trainer made us understand by giving real-time examples. Explains very calmly even if we ask a silly doubt also. Overall experience was very nice, the industry gap is filled between the academics and industry.

Rashmi, PD Engineer, Aricent

I Have done a Physical design course in ChipEdge. Mostly all the concepts I learned through practical labs with the help of trainers. Trainers are from product based company with more than 10 years experience. One Good Thing is, they have provided an individual license for all to practice the tool, which has a VPN facility. Through ChipEdge placement assistance, I got placed in Moslogi.

Ajay, PD Engineer, Moslogi

My expectation to join this course was to get into the PD domain and Yes, it met my expectations. The trainer is excellent and he answered all types of queries I asked. The materials provided are good and helped to crack the interviews. After doing this course it helped me to get into PD domain.

Haritha, PD Engineer, Synapse

I wanted to switch my current profile, the reason being the learning curve and career growth. I have to agree that the course has enabled me to fill in the gaps. This is a well-organized and well-implemented course structure. The trainer is very good at all the PD without a surprise and the way he gives the examples at different interview scenarios is very helpful. The quality materials are very well organized and really helpful for the ongoing preparation. VPN is another best thing I like about this institute. Really thankful for the support.

Praveen, PD Engineer, Aricent

Frequently Asked Questions (FAQs)

Training is delivered in Instructor Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login into the chipedge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course  will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge  trainers are typically having 10 to 20  years of VLSI industry experience and currently working in latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves. 

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences  is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short / long). please check “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs.  please check with our Course Counsellors. 

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

Course completion certificates will be provided, whoever meets the course completion criteria.

Enquire Now
  • 12 WeeksDURATION:
  • June 20, 2020STARTS FROM:

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