Course Overview:

The Physical Design Full-time course is designed for students looking to get comprehensive training that covers all the topics needed to start in the VLSI industry as a Physical Design Engineer. The course is designed by keeping the latest industry requirements in mind and will be covered by trainers experienced in Physical Design. All the relevant concepts, the latest methodologies, the support functions required as well as placement specific coaching will be provided over the duration of the course. More than 60% of the time will be utilized for hands-on training along with multiple projects.

Course Highlights:

  • Trainer with 10+ years of solid Physical Design experience in Industry.
  • Synopsys IC Compiler ICC2,VCS,Design Compiler, starRC and Prime time tool
  • Additional Lab Hours (remote access) through VPN.
  • The course is designed by experts in Physical Design, as per the needs of the industry.
  • 70% of the course time on labs, to facilitate hands-on learning using tools.

Training Delivery Model:

  • Instructor-led classroom training sessions. – Mondays to Fridays
  • Each topic is followed by Lab sessions on that particular module.
  • 24/7 remote Lab access through VPN.
  • Closed group support with Trainers and Lab Assistants on WhatsApp and e-mail.

What You Will Learn:

  • You will get hands-on experience on the physical design flow, using industry standard Synopsys tools.
  • This should help to give you confidence, to execute block level physical design work which industry is looking for and try for physical design positions.

Soft Skills Training & Mock Interviews

  • Soft skills training by leading corporate soft skill trainers.
  • Mock Interviews from the Senior  Industry Professionals.

Training Materials:

  • Training Materials will be provided,through LMS (online learning management system) which can be accessed online any time, any device.
  • Integrated Online Learning Management System where all reference materials and performance tracking will be available for every student.

Who Can Join This Course

  • Graduate Freshers(B.E/ in ECE/EEE/Instrumentation/Telecom who have graduated in 2018 or later.
  • Post-Graduate Freshers (M.Tech) with specializations like VLSI/Embedded/Power Electronics/Communications/Instrumentation..etc. who have graduated in 2018 or later.
  • Experienced Engineers / Faculty who have graduated in 2017 / earlier, but has some industry (any) / teaching experience and interested to switch to VLSI industry.  And are interested in doing a full time course, than weekend.

Admission Criteria

ChipEdge follows a comprehensive selection criterion for each candidate. The selection process consists of

  • Written Test (online) – Syllabus includes Aptitude, Digital Electronics, CMOS fundamentals,  Verilog ..etc.
  • Interview – Face to Face interview, to assess the fundamentals knowledge, learning ability, passion for VLSI, suitability for VLSI industry, communication skills, attitude, can be trained / not.

Course Syllabus:

Module 1 : Introduction to Linux and GVIM

Linux introduction, File structure, Commands :  pwd, ls, cd, mkdir, rmdir,rm,mv, cp, cat , more, less, head, tail, ps, kill, date, uptime, whoami, df, du, chmod, grep, pipes.

Introduction to GVIM & practice of commands. 

Module 2: CMOS fundamentals

Device Characteristics, Power Sources, Thevenin’s and Norton’s theorem, Semiconductor Device Physics.  BJT, MOSFET : Working and I-V Characteristics. CMOS : Logic Gates and Boolean Expression Implementation, Stick Diagram, CMOS Logic Gate Parameters

Semiconductor Processing Methods, Second Order Effects in CMOS Technology. 

Module 3 : Digital Electronics 

Number Theory, Boolean Algebra, K-map, Combinational circuits and Sequential circuits. 

Module 4 : Digital Design using Verilog

Overview of Digital Design with Verilog HDL, kinds of modeling styles: gate-level, dataflow, and behavioral. Language Constructs and Conventions. Few programming examples. 

Module 5 : Synthesis 

Review of ASIC Design flow & role of Synthesis, Synthesis flow, writing timing constraints in SDC format, constraining the design for timing, power, area goals, set optimization techniques, synthesize the design, Low power synthesis using UPF, generate and analyze the reports, save the netlist, SDC and interface files.

Module 6 :  Logic Equivalence Checking (LEC)

Formal Verification, Understanding & Matching compare points, Debugging non equivalent points, What-If Analysis.

Module 7 : TCL Scripting

Introduction to TCL, TCL commands, Variables, special characters, arithmetic expressions, regular expressions, Procedures, conditional branching : if-then-elseif, switch, looping: for, foreach, while, Break and continue. Working with lists and arrays. 

Scripting exercises from simple problem to complex automation problems, in an incremental manner and using the tools like Design Compiler, Prime Time, ICC2.

Module 8: Introduction to Physical Design, Inputs & Sanity Check

Introduction to physical design, Physical Design Flow, 

Data preparation : Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input, Sanity checks. 

Module 9 : Floorplan

Goals of Floorplanning, different aspects of floor planning, Rectangle/Rectilinear floorplans, Die size estimation (Core Utilization, Aspect ratio), IO placement, macro placement and guidelines,  channel-width estimation. 

Module 10 : Power Routing:

Goals of Power Routing, Power distribution structure (Rings, straps and follow-pin/std cell rail), metal stack information, power planning methodology, IR drop analysis, types of power consumption. Why Low power and low power techniques. Electro-migration analysis. 

Module 11 : Placement

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, placement optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Path Grouping and creating Bounds.

Module 12 : Timing Analysis (Pre Layout STA) & Optimization

STA Overview and concepts, Basic timing checks (setup, hold), understanding timing constraints(SDC), timing corners, timing report analysis, 

General optimization techniques, typical causes for timing violations and strategies for fixing the same, Pre-CTS optimization to Fix setup violations. 

Module 13: Clock Tree Synthesis (CTS)

Goals of CTS, Types of Clock-tree, constraints for CTS, building clock tree, Analyze the results,

Post-CTS optimization : Fixing Setup and Hold violations.   

Module 14: Routing

Goals of Routing, Stages of Routing:  Global Routing, Track assignment and Detail Routing, Routing options, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results. 

Module 15: Post Layout STA

Post layout STA using SPEF, Multi Mode Multi Corner STA, Derating factors, PVT, OCV, AOCV & POCV Variations, Crosstalk & Noise Analysis.

Module 16 :  ECO Flow

What is ECO, Types of ECO, Timing & Functional ECO prep, Performing the ECO placement and routing. 

Module 17 :  Sign-off Checks

Physical Verification (DRC, LVS, ANT, ERC, DFM), STA, IR drop analysis, Electro-Migration Analysis.

Module 18 : Projects

Projects will be given converging Netlist to GDS II flow.  Various projects that will allow the students to understand the intricacies of implementation for minimum area, low power, high performance. The method of execution will be similar to typical block level Physical Design work/project in the industry.  Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks. 

ChipEdge uses latest versions of below synopsys tools for different modules of the course. Each Student gets dedicated license for full day.

  • Digital Design with Verilog:  VCS
  • Synthesis – Design Compiler Topographical
  • LEC : Formality
  • Static Timing Analysis(STA): Prime Time SI
  • Physical Design:  IC Compiler 2 (ICC2)
  • RC Extraction: Star RC
  • Physical Verification: IC Validator
  • Synopsys ICC2 is a leader in Physical Design tools and used by the majority of the MNCs/ product companies in Bangalore / India
  • Additional Lab Hours through VPN, to enable you to spend more time on labs from home.


  • The trainer is working as Lead Physical Design Engineer with a leading VLSI Company in Bangalore and has 10+ years of Physical Design experience in VLSI industry, with multiple complex tape outs to his credit. He is passionate about teaching and mentoring many entry / mid-level engineers throughout his corporate career. He is an excellent Trainer and has received good credentials for all his training deliveries. He is dynamic in nature and brings high energy levels to the class.
  • The additional trainer is an experienced teacher, with a rich experience in teaching and mentoring entry-level engineering students. His passion and dynamism had received excellent feedback from his students.


  • Multiple evaluation tests both for performance in course subjects as well as readiness for physical design jobs and placement readiness.
  • Certification from Chipedge Technologies Private Limited, for  all eligible students, who meets course completion criteria, which includes attendance, completing the assignments, final written test, Final project assessment.  Grade will be given as per the performance in these tests.

Enquire Now
  • 5 MonthsDURATION:
  • 6th July 2020STARTS FROM:

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