Course Overview:

The Physical Design Full-time course is designed for students looking to get comprehensive training that covers all the topics needed to start in the VLSI industry as a Physical Design Engineer. The course is designed by keeping the latest industry requirements in mind and will be covered by trainers experienced in Physical Design. All the relevant concepts, the latest methodologies, the support functions required as well as placement specific coaching will be provided over the duration of the course. More than 60% of the time will be utilized for hands-on training along with multiple projects.

Course Highlights:

  • Trainer with 8+ years of solid Physical Design experience.
  • Synopsys IC Compiler ICC2 toolset will be used.
  • Additional Lab Hours (remote access) through VPN.
  • The course is designed by experts in Physical Design, as per the needs of the industry.
  • 60% of the time on labs, to facilitate hands-on learning using tools.
  • Cost effective and value for money.

Training Delivery Model:

  • Instructor-led classroom training sessions. – Mondays to Fridays
  • Each topic is followed by Lab sessions on that particular module.
  • 24/7 remote Lab access through VPN.
  • Closed group support with Trainers and Lab Assistants on WhatsApp and e-mail.

What You Will Learn:

  • You will get hands-on experience on the physical design flow, using industry standard Synopsys tools.
  • This should help to give you confidence, to execute block level physical design work which industry is looking for and try for physical design positions.

Training Materials:

  • Physical Handouts of Training Materials will be provided to all students.
  • Integrated Online Learning Management System where all reference materials and performance tracking will be available for every student.
  • Multiple evaluation tests both for performance in course subjects as well as self-evaluation for placement readiness.

Who are eligible for the course

  • Graduate Freshers in Electronics & Communication Engineering(BE/B.Tech)who have graduated in or after 2016 looking to start their careers in VLSI as a Verification Engineer.
  • Post-Graduate Freshers in Electronics & Communication Engineering (M.Tech) with specializations like VLSI, Instrumentation and Embedded Systems etc. who have graduatedin or after 2017.
  • Experienced graduates/post-graduates with the above mentioned qualifications who wish to change into the VLSI Verification domain.

Selection Criteria

ChipEdge follows a comprehensive selection criterion for all candidates. Candidates, especially freshers are selected considering their prior academic performances, knowledge of fundamentals and ability to perform successfully in placement interviews. The selection process consists of

  • General Evaluation Test – Covering fundamentals required for the VLSI industry as well as Aptitude.
  • Face to Face interviews with all candidates.

Tools to be used:

  • Synopsys IC Compiler (ICC2) Physical Design Toolset.
  • Synopsys ICC2 is a leader in Physical Design space and used by the majority of the MNCs/ product companies in Bangalore / India
  • Additional Lab Hours through VPN, to enable you to spend more time on labs from home. This is on top of Trainer led lab sessions during Sundays
  • Participants need to have own laptops to access the lab from home.

Course Outline:

Module 1 : Introduction to Linux and GVIM
  • Introduction to Linux and GVIM commands.
Module 2: Digital Electronics
  • MOS Operation, I-V Characteristics of MOS, Inverter Operation, NAND/NOR CMOS Circuits, MOS Second-order Effects.
  • Number Theory, Boolean Algebra, K-map, Combinational circuits, and Sequential Circuits.
Module 3: CMOS fundamentals
  • MOS Operation, I-V Characteristics of MOS, Inverter Operation, NAND/NOR CMOS Circuits, MOS Second-order Effects.(Verilog)
Module 4: Overall ASIC design Flow, Physical Design flow
Module 5: Inputs & Sanity Check
  • List of inputs (libraries, technology files, netlist, timing constraints) to the PD/Low power flow.
  • Contents of each input and sanity checks.
Module 6: Floorplan
  • Goals of floor planning, different aspects of floor planning
  • Area estimation, Square/Rectangle/Rectilinear Floorplans
  • IO placement, Macro placement
  • Data flow diagram
  • The orientation of the macros, in which scenario which blockage (soft/hard) have to be used
  • Channel-width estimation
  • Floorplanning guidelines.
Module 7: Power Routing:
  • Goals of Power Routing
  • Power plan parameters, On what base power plan/structure will be decided by the power team
  • PG Mesh and follow-pin/std cell rail
  • Low power domain creation (always on power domain/switchable power domain) power island creation
Module 8: Placement
  • Goals of Placement, Types of placements
  • Pre-place (End-cap, Tap & I/O Buffer) cells
  • Pre-place optimization, and in-place optimization
  • Congestion analysis, Timing analysis
  • Tie-cells, High-Fanout Net Synthesis
  • Scan chain re-order, Rejoining/Grouping/Bounds
Module 9: Clock Tree Synthesis (CTS)
  • Goals of CTS, Types of Clock-tree
  • CTS Specification, Building Clock tree, Analyze the results
  • Issues in routing and guidelines for optimum routing results
Module 10: Routing
  • Goals of Routing, Types-of Routing, Global Routing, Detail Routing
  • Fixing of routing violations (DRC, LVS), post route optimization
  • Fixing of routing violations (DRC, LVS), post route optimization
Module 11: Timing Analysis & Optimization
  • Basic timing checks (setup, hold), understanding timing constraints(SDC)
  • Timing corners, Timing report analysis, General optimization techniques
  • Typical causes for timing violations and strategies for fixing the same.
Module 12: Sign-off Checks
  • Physical Verification (DRC, LVS, ANT, ERC, DFM), IR drop analysis
  • Electro-Migration Analysis, Cross-Talk(SI) analysis
Module 13: Sign-off STA
  • STA Overview and concepts
  • Post layout STA using SPEF, Multi-Mode, Multi-Corner STA
  • Derating factors, OCV, AOC & POCV Variations
  • Crosstalk & Noise Analysis
  • Timing ECOs generation
Module 14: ECO Flow
  • What is ECO, Types of ECO, Timing & Functional ECO prep
  • Performing ECO placement and routing
Module 15: LEC
  • Physical Verification (DRC, LVS), Sign-off Timing analysis
  • Understanding & Matching compare points
  • Debugging non-equivalents
Module 16: Scripting
  • Basics of TCL, How to write scripts in TCL
  • How to understand complex TCL scripts and debug/modify them as needed
  • Best practices in writing TCL scripts
  • How to develop own commands, for your custom requirements
Module 17: Project

3 – 4 projects will be given converging Netlist to GDS II flow. Various projects that will allow the students to understand intricacies of implementation for min area, low power, high performance. The method of execution will be similar to a typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks.


      • The trainer is working as Lead Physical Design Engineer with a leading VLSI Company in Bangalore and has 8+ years of Physical Design experience in VLSI industry, with multiple complex tape outs to his credit.He is passionate about teaching and mentoring many entry / mid-level engineers throughout his corporate career. He is an excellent Trainer and has received good credentials for all his training deliveries. He is dynamic in nature and brings high energy levels to the class.
      • The additional trainer is an experienced teacher, with a rich experience of teaching and mentoring entry-level engineering students. His passion and dynamism had led to excellent feedback from his students with many going on to have a very successful professional career.

Soft skills training by leading corporate soft skill trainers.


      • Certification from Chipedge Technologies Private Limited.
      • Course learning assessment will be based on Blooms Taxonomy.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

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