Low Power Implementation (PD) using UPF

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Most of the chips in mobile / portable devices are low power intensive, designed using advanced low power techniques, which include multi-voltage, power gating, multi-VT ..etc.  And these low power specs are catpured in UPF/CPF formats.

The Physical Design (PD) engineers find it difficult, unless they understand these low power techniques and associated terminology (level shifters, isolation cells, state retention cells..) using CPF/UPF formats with respective tools.

This course is designed to help PD engineers understand low power implementation aspects, to be able to handle low power designs better and be successful in their roles.

Training Delivery Model:

  • Lecture & Lab sessions go hand in hand, like corporate training.
  • Sessions will be interactive in nature.
  • Physical Design (PD) Engineers with a minimum 1 year of hands on PD experience using ICC / Cadence Encounter / innovus
  • Technical Managers who want to learn Low power implementation flow

Course Content outline:

Module 1: Low power basics

Significance of Low power designs – Use cases; Types of power dissipation; LP Techniques- Power gating, Clock gating, DVFS, Multi-VDD, Multi VT; Power management cells & usage – ISO, LVL, P-Switch, RET, AON

Module 2: UPF

Why UPF, Power domains, Power state table, Power gating strategies, LVL-ISO strategies, SRSN, Activity – Developing UPF on sample design

Module 3: Low power implementation techniques

P-Switch Daisy chain, Voltage area, ISO-LVL placement, MV-CTS, AON buffering & feedthrough, ECO implementation, Leakage recovery, Dynamic power optimization

Module 4: Low power checks

Introduction to Inrush current analyses and low power signoff checks  – Demo of rules in ICC (Power intent checks, Implementation checks)

**Each module has associated labs and will be practiced immediately after lecture session. 

**Lab & Course is limited to only block level

Tools to be used:

  • Synopsys IC Compiler (ICC) with UPF 2.0

Assessment & Certification:

  • Course completion certificate from ChipEdge.
  • At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
  • Certification and Course Credits leading to M.S. degree, from Global University of Engineering, USA

Trainer:

Trainers are  having 8+ years of strong Physical Design on low power intensive designs. Till recently they were with INTEL and  has worked on multiple low power designs using UPF with ICC.  They have passion for teaching.

They are co-founders of VLSI Services company, offering services on PD ..etc.

FEE:

      • ₹ 25,000 (15% Service Taxes Extra)

Group Discount:

      • 2% discount on total fee for 3 or more participants joining together

Lessons