Most of the chips in mobile / portable devices are low power intensive, designed using advanced low power techniques, which include multi-voltage, power gating, multi-VT ..etc. And these low power specs are catpured in UPF/CPF formats.
The Physical Design (PD) engineers find it difficult, unless they understand these low power techniques and associated terminology (level shifters, isolation cells, state retention cells..) using CPF/UPF formats with respective tools.
This course is designed to help PD engineers understand low power implementation aspects, to be able to handle low power designs better and be successful in their roles.
Training Delivery Model:
- Lecture & Lab sessions go hand in hand, like corporate training.
- Sessions will be interactive in nature.
Course Content outline:
Tools to be used:
- Synopsys IC Compiler (ICC) with UPF 2.0
Assessment & Certification:
- Course completion certificate from ChipEdge.
- At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
- Certification and Course Credits leading to M.S. degree, from Global University of Engineering, USA
Trainers are having 8+ years of strong Physical Design on low power intensive designs. Till recently they were with INTEL and has worked on multiple low power designs using UPF with ICC. They have passion for teaching.
They are co-founders of VLSI Services company, offering services on PD ..etc.
- ₹ 25,000 (15% Service Taxes Extra)
- 2% discount on total fee for 3 or more participants joining together