24/7 VPN Access - Weekday & Weekend Classes - Experienced Trainers

ASIC Design Verification

Course Overview:

This course is designed and will be delivered by practicing experts in Verification, as per the industry requirements. Importance is given to cover the concepts, methodology and good emphasis on hands on training, with at least 60% of time allocated to the guided lab sessions and a project to be done by the participants.

Training Delivery Model:

  • Weekends (Saturdays) : Instructor-Led classroom training
  • Each Lecture session will be followed by Labs on that module
  • Weekdays : Lab support through Email and WhatsApp
  • Flexible learning with 24/7 Lab Access from home through VPN

Training Materials:

  • Hand-outs of training materials will be provided
  • Reference Materials will be shared

Who Can Attend This Course?

      • Working Professionals from VLSI industry, currently working in some area (RTL Design, FPGA Design, Synthesis, STA, board level testing..etc) , but want to switch to VLSI Verification.
      • Mtech, Btech Students desiring to build their careers in VLSI verification.
      • Faculty working in engineering colleges desiring to understand the industry flows and methodologies in verification.
      • Currently working Electrical and electronics engineers desiring to make a career in VLSI verification.

Pre-Requisites:

Knowledge on below topics are Required.

  1. Working knowledge of linux.
  2. Knowledge of Digital Electronics fundamentals.
  3. Knowledge of Verilog and ability to design circuts using Verilog.

Course Outline:

 

Part – 1 – Basic Verification:

Module 1: Introduction to Basic Verification Flow

ASIC flow, Verification flow, RTL Quality checking and Verification planning.

Module 2: Testbench Architecture Basics

General Test bench Architecture and Verification plan creation

Module 3: Verification Matrices for Chip Sign-off

Verification coverage, System Verilog assertions and Verification metrics.

Module 4: Complete Verification Environment

Project

 

PART 2 – Basic System Verilog

Module 5: Introduction to System Verilog

Overview of HDL and HVL, Need for SystemVerilog, SV capabilities and highlights, SV as one solution HDVL.

Module 6a: System Verilog Basics

Lexical Conventions, Data types, Aggregate Data types, Casting, SV operators and their precedence. Processes, Understanding the Procedural statements and control flow, process execution threads and fine grain process controls. Interfaces and Modports, Virtual interfaces, Clocking blocks

Module 6b: Design and verification building blocks

Module, program, interface, subroutines, packages, configurations, compilation and elaboration, declaration name spaces, Simulation time, time units and time precision

Module 7: SV Classes and Randomization and constraints

Classes, objects, handles and built-in methods for efficient TB development. Efficient memory management in SV. Different randomization techniques and constructs. Inline randomization, seeding, random methods and random stability.

Module 8: Riding SV on Chariot of OOPs

Tasks and functions and their enhancements in system Verilog. Introduction to OOP concepts of data abstraction, data encapsulation, data hiding, inheritance and polymorphism.

Module 9: Coverage based Verification

Introduction to code and functional coverage. Functional coverage in SV. Cover groups, cover points, cover bins and cross coverage constructs. Different ways of sampling the coverage and measuring the verification closure.

 

PART-3 – Advanced System Verilog

Module 10: Specialised communication packing and bug isolation in SV

Interprocess Synchronization and communication – Semaphore, Mailboxes and Named Events, Scheduling semantics Event-based simulation scheduling semantics— System Verilog’s stratified event scheduling algorithm— Determinism and non-determinism of event ordering— Possible sources of race conditions— PLI callback control points

Module 11: Faster verification using System Verilog Assertions

Introduction to Assertions. Advantages of assertions. Immediate and concurrent assertions. Writing assertion Sequences, Different ways of writing assertions and its constructs and calling methods.

Module 12: Application Programming Interfaces

Introduction to DPIs, DPI layers, importing and exporting mechanism from System Verilog to other language. Usage and advantages of using DPIs and its Limitations.

 

Part-4 – UVM

Module 13: Verification Methodology, UVM Basics

Need for a Verification methodology, UVM as a template, introduction and evolution of UVM. Basic concepts of UVM.

Module 14: UVM Components, Agents, Sequencer, Sequence. Macros, TLM

Understanding UVM Test Bench – Objects, Components – Drivers, Sequencers, Sequences, Sequence item, Monitors, transactions, Introduction to Macros, Configuration Database, Resource Database. Introduction to Transaction Level modeling, Concept of TLM in UVM. TLM communications and connections – Interfaces, Ports, Exports, Imps, Analysis Ports, Building test bench for a real time design with these UVM components.

Module 15: UVM Phasing, UVM Factory and Advanced sequence control

Need for Phasing, Importance of phases and usage of phases in a typical Test Bench environment, Common Phases, Run time phases, User-Defined Phases.Introduction to Factory, Importance of dynamic binding and factory usage. Registering , creating and configuring with Examples. Handling and triggering multiple sequences and sequence body methods efficiently. Virtual Sequences

Module 16: Register Modeling using UVM Register Layer

UVM Register Layer, Blocks, Address maps, Register Files, Registers, Fields, DUT Integration – Register Adapter, Register Sequences, Predictor Classes.

Module 17: Reporting, UVCs

Reporting in UVM, different verbosity and log controls. Introduction to UVC. Guidelines and rules. UVC environment, UVC layering, Real time example of UVC.

Module 18: Complete UVC building

For a given Design, building an UVC – using best practices, developing fully configurable, reusable UVC and UVM Test Bench environment.

Tools to be used:

  • Simulator and linting tools shall be used.
  • At least 3 hrs of labs/day through out the course.
  • Additional Lab Hours through VPN, to enable you spend more time on labs from home. This is on top of Trainer led lab sessions during Sundays.

Trainer:

Trainer is a working professional with hands on VLSI verification and training experience of 10+ years.

Trainer is passionate about teaching and mentored many engineers throughout his career.

  • Excellent Trainer and has received good credentials for all training deliveries
  • dynamic in nature and brings high energy levels to the class.

Certifications:

  • Course learning will be assessed as per Bloom’s Taxonomy
  • Course completion certificate from ChipEdge

 

 

 

 

 

Lessons