Course Overview

Design For Testability is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects.  With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, Design For Testability has evolved as a specialization in itself over a period of time. Engineers work on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.

The course is designed and will be delivered by experts in DFT, as per current industry project requirements.  The importance is given to cover the concepts, methodology thoroughly with the right emphasis on hands-on training, using Synopsys DFT tools with at least 50 % time allocated to lab sessions.

Learning Outcome

At the end of this course, the candidate will be able to:

  • Review, analyze, and propose changes to improve testability and implement them.
  • Analyze test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
  • Generate the patterns for both stuck-at and at-speed testing of the design for optimal test cost.
  • Validate the patterns in a pre-silicon simulation environment
  • Understanding and applying debugging techniques used in debugging test on silicon in a simulation environment

Training Delivery Model

  • Instructor-led classroom training sessions. – Monday to Friday
  • Each topic is followed by Lab sessions on that particular module.
  • Closed group support with Trainers and Lab Assistants on WhatsApp and e-mail.

Who Can Attend This Course

  • Fresh Graduates (B.E/B.tech) in ECE/EEE/Instrumentation/Telecom who have graduated in 2019 or later.
  • Post-Graduate Freshers (M.Tech / M.Sc) with specializations like VLSI/Embedded/Power Electronics /Communications/Instrumentation..etc. who have graduated in 2019 or later.
  • Experienced Engineers / Faculty who have graduated in 2018/ earlier, but have some industry (any) / teaching experience and interested to switch to VLSI industry.  And are interested in doing a full-time course, then a weekend.

Pre-requisites

  • Knowledge of Digital Design.
  • Knowledge of ASIC / SOC design flow.
  • Prior knowledge of DFT is not required

Tools to be used

ChipEdge uses the latest versions of Synopsys tools for different modules of the course. Each Student gets a dedicated license during the lab.

Below is the list of Synopsys tools to be used for each module.

  • DFT Compiler – For Scan Insertion
  • BSD Compiler – For Boundary Scan Insertion
  • TetraMax  — For ATPG  / pattern Generation
  • VCS  — For Simulations and Debugging

Curriculum

Module1: Introduction To DFT, DFT Basics

  • ASIC Flow
  • DFT Basics
  • Chip Fabrication Process
  • ATE Basics

Module2: Scan Insertion

  • Scan architecture overview
  • Scan Design Basics
  • Scan Golden Rules
  • Scan DRC Checks
  • Scan Insertion
  • Generate test protocol and understanding
  • Lock-Up Latches

Module 3: Scan Compression

  • Basics/Need for Compression
  • Compression Techniques
  • On-Chip-Clocking
  • At-Speed Testing

Module4: Hierarchical Scan And Boundary Scan

  • Hierarchical Scan
  • Bscan (Boundary Scan)
  • Jtag 1149.1

Module5: Introduction To ATPG, Atpg Basics

  • ATPG Basics
  • Faults Collapsing
  • ATPG Algorithms

Module6: Fault Models, Fault Classes

  • Fault Models,
  • ATPG DRC,
  • Fault Classes,
  • ATPG

Module7: Pattern Generation And Simulations

  • Simulation Basics
  • Atpg Simulations
  • Coverage Improvement

Module8: At- Speed ATPG And Simulations

  • At-Speed ATPG
  • LOC and LOS
  • At-Speed Simulations

Module9: Simulations And Debugging

  • Scan Simulations Debug
  • Diagonsis Flow
  • Fault Simulation

Module10: BIST

  • BIST Architecture,
  • Memory BIST
  • Logic BIST

Module11: Project

Trainer

The trainer has 19+ years of VLSI Industry Experience, with substantial experience in DFT and currently working as a manager in a Product company. He is passionate about teaching & sharing his knowledge and mentored entry/mid-level engineers throughout his career.

Certifications

Multiple evaluation tests both for performance in course subjects as well as readiness for Design for test jobs and placement readiness.

Certification from Chipedge Technologies Private Limited, for all eligible students, who meet course completion criteria, which includes attendance, completing the assignments, final written test, Final project assessment.  The grade will be given as per the performance in these tests.

Placement Assistance

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

Integrated Internship

Internship option available for M.tech students. please check with our Course Advisor for details.

Course Fee

Connect with our career advisor for fee & discount offer.

Easy EMI Option Available
Pay in Easy Installments at no extra cost

Demo videos

A small clip from the recent online lecture session

Lab Session

A small clip from the recent online lab session

Trainee Video Reviews

Reviews

Frequently Asked Questions (FAQs)

The Minimum Qualification Required Is An Educational Background In Electronics.  This Could Include

  • B. Tech/B.E In ECE / EEE / Telecom / Instrumentation.
  • M.Tech/M.Sc In VLSI / Embedded / Power Electronics / Digital Electronics / Digital Communications.

Year of Passing:

  • For freshers without job experience:  2018 / 2019
  • For Engineers with experience in certain domains:  2017 or earlier.

We Provide Placement Assistance By Arranging Interview Opportunities With Hiring Companies. Every Trainee Gets A Minimum Of 4 Interview Opportunities To Prove Their Ability. To Ensure Successful Placement, We Provide Added Support Including Mentorship, Fundamentals Classes, Soft Skills Training, Mock Interviews Etc.

Service Companies Include Aricent, Altran, Sankalp Semi, Synapse, Cerium, Mindlance, Si2chip, Signoff Semiconductors Etc 

Product Companies (MNCs) Include Intel, Samsung, Synopsys, MediaTek, Global Foundries, Microsemi Etc.

Handouts of The Lecture Content and Lab Manuals Shall Be Provided Before Every Class Starts.

We use 28nm libraries for labs, projects.

We use the latest and genuine versions of Synopsys Tools for our courses. please check course pages, for the list of tools used for that course. We provide a dedicated tool license for every trainee during the lab/project work.

This is the biggest advantage with ChipEdge courses, as quality and standard EDA/VLSI tools are important for any VLSI course. And these tools are typically very costly ranging from $50,000 to $200,000 per license per year. Many service/product companies cannot afford these tools. Thanks to the EDA/Tool companies for giving these tools at subsidized & affordable rates to training companies, so that engineers can get trained on these tools.

All Our Trainers Have 10-20 Years Of Experience In The VLSI Industry. They Are Selected For Their Domain Expertise, Passion For Sharing Knowledge As Well As Excellent Teaching Skills.

Every Successful Student Will Receive A Course Completion Certificate From ChipEdge Subject To Their Performance During The Course.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs.  please check with our Course Counsellors. 

Yes, our online payment gateway accepts all credit, debit cards, net banking & UPI.  Our course counselors shall provide you details on the online payment process.

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  • 5 MonthsDURATION:
  • July 27, 2020STARTS FROM:

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