Design For Testability is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, Design For Testability has evolved as a specialization in itself over a period of time. Engineers work on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.
The course is designed and will be delivered by industry experts in DFT, as per current industry project requirements. The importance is given to cover the concepts, methodology thoroughly with the right emphasis on hands-on training, using Synopsys DFT tools with at least 50 % time allocated to lab sessions.
Blended Learning Model
- Learning (Theory + Labs) : 4 months (Online)
- Project (application of your learning): 1 month (Online / Class Room)
- Integrated Internship: 1 month (optional)
Training Delivery Model
Class Timings and Duration:
- Instructor-led Live-Online sessions.
- Sessions will be interactive, where you can ask questions during the session itself.
- Training will be 5 days per week – Monday to Friday
- 5 Hours per day including theory and lab sessions. 25Hours per week. Total of 550Hours of instructor-led Training.
- Each topic is followed by hands-on lab sessions with VLSI tools (Synopsys).
- Closed group support with Trainers and Lab Assistants on Whatsapp and email tech groups.
- All sessions (Lecture & Lab) will be recorded to view at a later time
At the end of this course, the candidate will be able to:
- Review, analyze, and propose changes to improve testability and implement them.
- Analyze test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
- Generate the patterns for both stuck-at and at-speed testing of the design for optimal test cost.
- Validate the patterns in a pre-silicon simulation environment
- Understanding and applying debugging techniques used in debugging test on silicon in a simulation environment
Soft Skills Training & Mock Interviews
- Soft skills training by leading corporate soft skill trainers.
- Mock Interviews from the Senior Industry Professionals.
- Training Materials will be provided, through LMS (online learning management system) which can be accessed online any time, any device.
- Course reference materials, videos ..etc will be provided through LMS.
Who Can Join This Course
- Graduate Freshers(B.E/B.tech) in ECE/EEE/Instrumentation/Telecom who have graduated in 2019 or later.
- Post-Graduate Freshers (M.Tech) with specializations like VLSI/Embedded/Power Electronics /Communications/Instrumentation..etc. who have graduated in 2019 or later
- Experienced Engineers / Faculty who have graduated in 2018/ earlier, but have some industry (any) / teaching experience and interested to switch to VLSI industry.
ChipEdge follows a comprehensive selection criterion for each candidate. The selection process consists of
- Written Test (online) – Syllabus includes Aptitude, Digital Electronics, CMOS fundamentals, introduction to Verilog.
- Interview – interview, to assess the fundamental knowledge, learning ability, passion for VLSI, suitability for VLSI industry, communication skills, attitude, can be trained / not.
For more information, please visit Admission Details
- Knowledge of Digital Design.
- Knowledge of ASIC / SOC design flow.
- Prior knowledge of DFT is not required