Design For Testability is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, Design For Testability has evolved as a specialization in itself over a period of time. Engineers work on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.
The course is designed and will be delivered by experts in DFT, as per current industry project requirements. The importance is given to cover the concepts, methodology thoroughly with the right emphasis on hands-on training, using Synopsys DFT tools with at least 50 % time allocated to lab sessions.
At the end of this course, the candidate will be able to:
- Review, analyze, and propose changes to improve testability and implement them.
- Analyze test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
- Generate the patterns for both stuck-at and at-speed testing of the design for optimal test cost.
- Validate the patterns in a pre-silicon simulation environment
- Understanding and applying debugging techniques used in debugging test on silicon in a simulation environment
Training Delivery Model
- Instructor-led classroom training sessions. – Monday to Friday
- Each topic is followed by Lab sessions on that particular module.
- Closed group support with Trainers and Lab Assistants on WhatsApp and e-mail.
Who Can Attend This Course
- Fresh Graduates (B.E/B.tech) in ECE/EEE/Instrumentation/Telecom who have graduated in 2019 or later.
- Post-Graduate Freshers (M.Tech / M.Sc) with specializations like VLSI/Embedded/Power Electronics /Communications/Instrumentation..etc. who have graduated in 2019 or later.
- Experienced Engineers / Faculty who have graduated in 2018/ earlier, but have some industry (any) / teaching experience and interested to switch to VLSI industry. And are interested in doing a full-time course, then a weekend.
- Knowledge of Digital Design.
- Knowledge of ASIC / SOC design flow.
- Prior knowledge of DFT is not required
Tools to be used
ChipEdge uses the latest versions of Synopsys tools for different modules of the course. Each Student gets a dedicated license during the lab.
Below is the list of Synopsys tools to be used for each module.
- DFT Compiler – For Scan Insertion
- BSD Compiler – For Boundary Scan Insertion
- TetraMax — For ATPG / pattern Generation
- VCS — For Simulations and Debugging