Design Verification (Advanced)

[rev_slider alias=”weekend-design-for-test-course”]

Course Overview:

Design For Testability (DFT) is a specialization in the SOC design cycle, which facilitates a design for detecting manufacturing defects.  With increase in size & complexity of chips, facilitated by advancement of manufacturing technologies, It has evolved as a specialization in itself over a period of time.  DFT Engineers,  works on introducing various test structures as part of the design flow, to increase the testability of logic, pads, memories, interconnects.

This course is designed for the working VLSI / Electronics engineers who want to learn / enhance their knowledge on Design For Testability (DFT) and become Skilled DFT engineers.

The course is designed and will be delivered by experts in DFT, as per current project requirements.  Importance is given to cover the concepts, methodology thoroughly with good emphasis on hands-on training, using Industry Standard DFT tools with at least 50 % time allocated to lab sessions.

A winner is someone who recognizes his God given talents, works his tail off to develop them into skills and use these skills to accomplish his goals. – Larry Bird

Duration & Timings:

  • 8 Weeks (Saturdays)
  •  10am – 6pm (including hands on labs)

Course Starting Date:     20th Aug (Saturday)

Training Location & Venue:

  • 2nd floor, Tapaswiji Arcade, Silk Board Junction. Bangalore.

Training Delivery Model:

  • Lecture & Lab sessions go hand in hand, like corporate training.
  • Sessions will be interactive in nature.

Training Material & Certification:

  • Hand outs of training material will be provided.
  • Course completion certificate from ChipEdge.
  • Course learning will be assessed as per Bloom’s Taxonomy.
  • 3 credit Course  leading to M.S degree and Certification from Global University of Engineering, USA.

Salient Features:

  • Trainer with 1o+ years of  Industry Experience and currently working.
  • Industry Standard DFT  tool set will be used.
  • 3 credit Course  leading to M.S degree and Certification from Global University of Engineering, USA.
  • Additional Lab Hours (remote access from home) through VPN.
  • Course designed by experts in DFT, as per the needs of industry.
  • 50% of time on labs, to facilitate hands on learning using tools.

 

Who Can Attend This Course:

  • Entry level / Experienced DFT engineers, who want to learn DFT in a systematic way from fundamentals to techniques, methodologies.
  • RTL Design, Verification, Synthesis, STA and Physical Design Engineers, CAD Engineers who need to understand DFT for effective integration into their respective design flows.
  • Application Engineers who need to understand DFT, for effective customer interactions & problem solving
  • Faculty working in Engineering Colleges, teaching VLSI subjects.
  • Anyone interested to learn basic to intermediate level of DFT concepts and tool flow.
  • M.tech (VLSI) Interns/Freshers/Students

Pre-requisites:

  • Knowledge of digital design.
  • Knowledge of ASIC / SOC design flow.
  • At least 1 year of work experience in ASIC or SOC Design Flow.
  • Prior knowledge of DFT is not required

 

More than 50% of course time on hands-on Labs, Project.  Each module has associated labs and practiced at end of lecture session.

Course Content outline:

Course – DFT (SCAN+ATPG)

Duration: 8 Weekends

SCAN & JTAG Insertion

Week 1:

  • Full ASIC flow – DFT
  • DFT Basics
  • Understanding of SCAN in depth
  • Scan architecture overview
  • Types of Scan
  • Scan golden rules

Week 2:

  • Understanding and analysis of DFT DRC
  • Multiple clock handling
  • DRC Fixing with examples
  • Full scan insertion and stitching without compression
  • Generate test protocol and understanding

Week 3:

  • Basics/Need of Compression
  • Compression techniques
  • Scan insertion with compression
  • On-chip clocking for at-speed testing

Week 4:

  • Hierarchical Scan Design
  • Top-Down Scan Insertion
  • Boundary scan basics
  • Boundary scan cell operation in detail
  • JTAG basics, operation and state machine
  • Understanding of P1500

ATPG & Diagnostics

Week 1:

  • DFT Overview – ATPG
  • Understanding of Defects and Faults
  • Types of fault models
  • Basic concepts of ATPG
  • ATPG algorithm
  • Different types of ATPG

Week 2:

  • Stuckat fault model with an example
  • Understanding of ATPG constraints
  • Understanding of SPF
  • ATPG DRC analysis
  • ATPG for Stuck-at fault model
  • Coverage improvement techniques

Week 3:

  • At speed fault models
  • Understanding Transition fault ATPG
  • ATPG setup for transition fault model
  • ATPG for Transition fault model
  • Path delay fault modelling
  • Pattern simulation

Week 4:

  • Introduction to Diagnosis
  • Diagnosis Flow
  • Analyzing failure logs
  • Chain Failure Diagnosis
  • Successful results

Learning Outcome:

At the end of this course, the candidate will be able to:

  • Read in the netlist that has DFT logic inserted in it and along with the various SPF files in the ATPG EDA tool.
  • Build the ATPG model.
  • Run DRC checks on the design.
  • Generate patterns for stuck-at and at-speed models.
  • Review Test Coverage & do incremental ATPG.
  • Write-out the patterns.
  • Diagnose failure logs provided by the ATE engineer

 

Tools to be used:

  • Industry Standard DFT Tool set will be used.
  • Additional Lab Hours through VPN, to enable you spend more time on labs from home. This is on top of Trainer led lab sessions during Sundays.

Assessment & Certification:

  • Course completion certificate from ChipEdge.
  • At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
  • 3 credit Course  leading to M.S degree and Certification from Global University of Engineering, USA.

 

Trainer:

The trainer has 10+ years of VLSI  industry Experience in DFT and Worked for companies such as Texas Instruments, Intel & Synopsys. He is passionate in teaching & sharing his knowledge and mentored entry / mid level engineers throughout his career.

He holds M.Tech. (Microelectronics) degree from IIT-Bombay and has two patents & multiple technical publications.

 

DFT Course Testimonials-

The quality of teaching is top notch. The trainer has answered all our queries with patience, clarity and enthusiasm. All has been done with extreme professionalism. Chipedge DFT program is very unique in a sense that a separate training program on DFT is very rare at least in India.

I feel fortunate to have found one such unique course and enrolled for it. The course has given a lot of exposure to DFT and broken my idea that DFT is an easy job to do.

– Vasanth, 9 years of RTL Design & Verification Experience and working for TechVulcan.

Trainer is very helpful even in very small and silly doubts explain everything asked to him. About course, it was very good. When I have started I have so many doubts but now at the end of this course doubts are clear with clear understanding of concepts.

…Hardik K , M.Tech Fresher, placed in “Imspired Solutions” as DFT Engineer

Trainer has good experience which helped us in all labs whenever we were stuck at some problems. Being a fresher, I don’t have any practical knowledge about DFT. Expectation was this course will help me build and improve my basics.

…S Kanjariya, M-Tech Fresher, Placed in “Imspired Solutions” as DFT Engineer

The trainer is good and has put his efforts to prepare the content and delivered the course very well.

…Kiran, 3+ yrs in DFT working on MBIST, with IBM.

It is a much needed course for every ASIC engineer. I am from FPGA background and I could realize the importance of DFT techniques for chip qualification.

I have joined the course to understand the basics of DFT and its implication to front end design. The purpose of LINT checks for DFT is understood. Considerable confidence is gained in DFT scan chain insertion, ATPG and MBIST DFT using tools.

– chandran , 8+ years of RTL Design, FPGA validation Experience.

No institute gives hands on training in DFT. Thanks to ChipEdge technologies team for providing this opportunity.I never worked on so many tools ever seriously and that too in reasonable price.

Trainer is great, anytime ready to solve problems, in and out of class, never gets irritated to our silly doubts, on top of it her experience in DFT is commendable. I recommend everyone who are curious to work or to explore in DFT , no other institute will match Chipedge.

– Ramesh, 1 year of internship in DFT.

The trainer is really good and has strong knowledge and expertise in DFT. Labs are designed very well, adequate with the course requirements.

…Amit, 2+ yrs of VLSI Experience with a EDA company.

I have joined to get Basic Understanding in DFT, along with advanced concepts. The course gave me good understanding of overall DFT with hands on experience with using industry level Mentor tools on SCAN, ATPG, MBIST, JTAG.

Trainer is excellent to present the subject to my understanding level and made me to understand from ground level to advanced concepts. The overall course is good and Labs are prepared in the methodical way.

– Nithin, 7 years of Physical Design experience.

Trainer helped in learning concepts very clearly .

…Balaji , M-Tech(VLSI), working as DFT Engineer

Tool access with VPN connectivity was really great.

…Rajiv, 9+ yrs of DFT Experience with internal tools with a MNC company.

Trainer is answered all questions with clarity and example

…Manju , 2+yrs in DFT with a service company.

Being a fresher I didn’t have knowledge about ATPG so I had to start from the scratch. So for me it would have been far much better than the level of teaching. Trainer was very supportive and answerable to all of the questions asked by us and tried to solve our doubts as much as possible.

…Rani , Asst. Professor in Engineering College

 

Investment Amount:

If a man empties his purse into his head, no one take it away from him. An investment in knowledge always pays best interest. Benjamen Franklin.

It would be right investment on this high quality course, with high ROI (return on investment) considering good opportunities available for experienced & quality DFT engineers.

Details:

  • Rs 44,000/ + 15% Service Tax ( for lump-sum payment)
  • Rs (24,000 + 24,000) +15% Service tax- (for two installment payment)
  • First installment due at registration, second before 5th Class.
  • For installment option, no discount given on the second installment.

Group Discount:

  • 3% discount on total fee for 3 or more participants joining together.

Payment:

  • Fee to be deposited in ChipEdge company account, using netbanking / cheque deposit. For company bank account details please contact admissions@chipedge.com and email deposit details to the same email account.

Registration

  • If interested to do this course, please Register below and send the payment details to admissions@chipedge.com . Your seat will be confirmed only after receiving the payment.

Contact Details:

For any further details on this course, please reach us on +91- 9611 766 442 or training@chipedge.com

Lessons