Course Overview

Design For Testability -DFT course is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects.  With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has evolved as a specialization in itself over a period of time. DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.

DFT Course is designed and will be delivered by experts in DFT, as per current industry project requirements.  The importance is given to cover the concepts, methodology thoroughly with right emphasis on hands-on training, using Synopsys Design For Testability (DFT) tools with at least 50 % time allocated to lab sessions.

Learning Outcome

At the end of this course, the candidate will be able to:

  • Review, analyze, and propose changes to improve testability and implement them.
  • Analyze test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
  • Generate the patterns for both stuck-at and at-speed testing of the design for optimal test cost.
  • Validate the patterns in a pre-silicon simulation environment
  • Understanding and applying debugging techniques used in debugging test on silicon in a simulation environment

Training Delivery Model

  • Instructor-Led Online Live Virtual classroom training
  • Timings9:30 am to 1 pm (Saturday & Sunday)
  • Module-specific Lecture sessions and Labs conducted hand-in-hand
  • Emphasis on Lab driven hands-on training aimed at building key skills
  • Weekdays: Lab support through Email and WhatsApp
  • Flexible learning with Lab Access from home through VPN

Training Materials

Soft copies of training materials will be provided, through LMS (online learning management system) which can be accessed online any time, any device.

Certification

DFT Course completion certificate will be provided, for all eligible candidates who meet the course completion criteria. The assessment process includes evaluating the assignments and final written test.

Pre-requisites

  • Knowledge of Digital Design.
  • Knowledge of ASIC / SOC design flow.
  • Prior knowledge of DFT is not required

Who Can Attend This Course

  • Entry-level / Experienced DFT engineers, who want to learn DFT systematically from fundamentals to techniques, methodologies.
  • RTL Design, Verification, Synthesis, STA, and Physical Design Engineers, CAD Engineers who need to understand DFT for effective integration into their respective design flows.
  • Application Engineers who need to understand DFT Course & Design for Test, for effective customer interactions & problem-solving
  • Faculty working in Engineering Colleges, teaching VLSI subjects.
  • Anyone interested to learn basic to intermediate level of DFT concepts and tool flow.

Educational Qualifications

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S  in VLSI / Embedded Systems / Electronics / Similar

Tools to be used

DFT Course & Design for Test Synopsys tool suite will be used, with one dedicated license for each trainee.

  • DFT Compiler – For Scan Insertion
  • BSD Compiler – For Boundary Scan Insertion
  • TetraMax  — For ATPG  / pattern Generation
  • VCS  — For Simulations and Debugging

Lab Access

  • Lab Access will be provided through a VPN.
  • Weekly 14 hours of Lab access is provided.
  • It can be accessed in 24×7 mode.
  • Can use, allocated usage limit anytime within the week.

Extra Lab Hours Per Week

  • If you need more than 14 hours of lab access per week, it is possible to provide at extra cost.
  • please get in touch with our course counselors, through Enquiry forms.

Curriculum

Module1: Introduction To DFT, DFT Basics
  • ASIC Flow
  • DFT Basics
  • Chip Fabrication Process
  • ATE Basics
Module2: Scan Insertion
  • Scan architecture overview
  • Scan Design Basics
  • Scan Golden Rules
  • Scan DRC Checks
  • Scan Insertion
  • Generate test protocol and understanding
  • Lock-Up Latches
Module 3: Scan Compression
  • Basics/Need for Compression
  • Compression Techniques
  • On-Chip-Clocking
  • At-Speed Testing
Module4: Hierarchical Scan And Boundary Scan
  • Hierarchical Scan
  • Bscan (Boundary Scan)
  • Jtag 1149.1
Module5: Introduction To ATPG, Atpg Basics
  • ATPG Basics
  • Faults Collapsing
  • ATPG Algorithms
Module6: Fault Models, Fault Classes
  • Fault Models,
  • ATPG DRC,
  • Fault Classes,
  • ATPG
Module7: Pattern Generation And Simulations
  • Simulation Basics
  • Atpg Simulations
  • Coverage Improvement
Module8: At- Speed ATPG And Simulations
  • At-Speed ATPG
  • LOC and LOS
  • At-Speed Simulations
Module9: Simulations And Debugging
  • Scan Simulations Debug
  • Diagonsis Flow
  • Fault Simulation
Module10: BIST
  • BIST Architecture,
  • Memory BIST
  • Logic BIST
Module11: Project

A block level design will be given as project, in which you need to insert scan and generate patterns, to get the required test coverage.

Trainer

The trainer has 19+ years of VLSI Industry Experience, with substantial experience in DFT and currently working as a manager in a Product company. He is passionate about teaching & sharing his knowledge and mentored entry/mid-level engineers throughout his career.

Course Fee

Actual Price:

  • Rs 60,000

Offer Price:

  • Rs 40,000  – without Lab extension after the last day of course work.
  • Rs44,000  – with Lab extension of 2 weeks after the last day of course work.
  • 18% of GST will be applicable.

No Cost EMI Option Available
Pay in Easy Installments at no extra cost

Payment Options

  • We accept all Credit/debit cards.
  • We do not accept any cash payments.

Lab Access

  • Weekly 14 hours of Lab access is provided.

Extra Lab Hours Per Week

  • If you need more than 14 hours of lab access per week like 20 / 30 / 40 hrs, it is possible to provide at extra cost.
  • For getting customized lab access, please get in touch with our course counselors, through enquiry forms.

Placement Assistance 

  • Chipedge provides placement help to all candidates by providing them industry interview opportunities.

Demo videos

A small clip from the recent online lecture session

Lab Session

A small clip from the recent online lab session

Trainee Video Reviews

Reviews

Frequently Asked Questions (FAQs)

Training is delivered in Instructor Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login into the chipedge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course  will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge  trainers are typically having 10 to 20  years of VLSI industry experience and currently working in latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves. 

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences  is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short / long). please check “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs.  please check with our Course Counsellors. 

Course completion certificates will be provided, whoever meets the course completion criteria.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

Enquire Now
  • 12 Weeks DURATION:
  • May 30, 2020STARTS FROM:

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