Design For Testability -DFT course is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has evolved as a specialization in itself over a period of time. DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.
DFT Course is designed and will be delivered by experts in DFT, as per current industry project requirements. The importance is given to cover the concepts, methodology thoroughly with right emphasis on hands-on training, using Synopsys Design For Testability (DFT) tools with at least 50 % time allocated to lab sessions.
At the end of this course, the candidate will be able to:
- Review, analyze, and propose changes to improve testability and implement them.
- Analyze test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
- Generate the patterns for both stuck-at and at-speed testing of the design for optimal test cost.
- Validate the patterns in a pre-silicon simulation environment
- Understanding and applying debugging techniques used in debugging test on silicon in a simulation environment
Training Delivery Model
- Instructor-Led Online Live Virtual classroom training
- Timings: 9:30 am to 1 pm (Saturday & Sunday)
- Module-specific Lecture sessions and Labs conducted hand-in-hand
- Emphasis on Lab driven hands-on training aimed at building key skills
- Weekdays: Lab support through Email and WhatsApp
- Flexible learning with Lab Access from home through VPN
Soft copies of training materials will be provided, through LMS (online learning management system) which can be accessed online any time, any device.
DFT Course completion certificate will be provided, for all eligible candidates who meet the course completion criteria. The assessment process includes evaluating the assignments and final written test.
- Knowledge of Digital Design.
- Knowledge of ASIC / SOC design flow.
- Prior knowledge of DFT is not required
Who Can Attend This Course
- Entry-level / Experienced DFT engineers, who want to learn DFT systematically from fundamentals to techniques, methodologies.
- RTL Design, Verification, Synthesis, STA, and Physical Design Engineers, CAD Engineers who need to understand DFT for effective integration into their respective design flows.
- Application Engineers who need to understand DFT Course & Design for Test, for effective customer interactions & problem-solving
- Faculty working in Engineering Colleges, teaching VLSI subjects.
- Anyone interested to learn basic to intermediate level of DFT concepts and tool flow.
- B.E / B.Tech in Electronics / Electrical / Instrumentation
- M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar
Tools to be used
DFT Course & Design for Test Synopsys tool suite will be used, with one dedicated license for each trainee.
- DFT Compiler – For Scan Insertion
- BSD Compiler – For Boundary Scan Insertion
- TetraMax — For ATPG / pattern Generation
- VCS — For Simulations and Debugging
- Lab Access will be provided through a VPN.
- Weekly 14 hours of Lab access is provided.
- It can be accessed in 24×7 mode.
- Can use, allocated usage limit anytime within the week.
Extra Lab Hours Per Week
- If you need more than 14 hours of lab access per week, it is possible to provide at extra cost.
- please get in touch with our course counselors, through Enquiry forms.