Course Overview:

Design For Testability (DFT) is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects.  With the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has evolved as a specialization in itself over a period of time.  DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.

The course is designed and will be delivered by experts in DFT, as per current industry project requirements.  Importance is given to cover the concepts, methodology thoroughly with right emphasis on hands-on training, using Synopsys DFT tools with at least 50 % time allocated to lab sessions.

Learning Outcome:

At the end of this course, the candidate will be able to:

  • Review, analyse and propose changes to improve testability and implement them.
  • Analyse test coverage, propose changes to improve test coverage to achieve the goal with optimal patterns
  • Generate the patterns for both stuck-at and at speed testing of the design for optimal test cost.
  • Validate the patterns in pre-silicon simulation environment
  • Understanding and applying debugging techniques used in debugging test on silicon in simulation environment

Training Delivery Model:

  • Instructor-led classroom training sessions. – Mondays to Fridays
  • Each topic is followed by Lab sessions on that particular module.
  • 24/7 remote Lab access through VPN.
  • Closed group support with Trainers and Lab Assistants on WhatsApp and e-mail.

Who Can Attend This Course:

  • B.Tech or M.Tech Freshers/Students/Interns looking to start a career in VLSI.
  • Entry level / Experienced DFT engineers, who want to learn DFT systematically from fundamentals to techniques, methodologies.
  • RTL Design, Verification, Synthesis, STA and Physical Design Engineers, CAD Engineers who need to understand DFT for effective integration into their respective design flows.
  • Application Engineers who need to understand DFT, for effective customer interactions & problem-solving
  • Faculty working in Engineering Colleges, teaching VLSI subjects.
  • Anyone interested to learn basic to intermediate level of DFT concepts and tool flow.


  • Knowledge of Digital Design.
  • Knowledge of ASIC / SOC design flow.
  • Prior knowledge of DFT is not required

Educational Qualifications

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S  in VLSI / Embedded Systems / Electronics / Similar

Course Syllabus:

Module1: Introduction To DFT, DFT Basics

  • ASIC Flow
  • DFT Basics
  • Chip Fabrication Process
  • ATE Basics

Module2: Scan Insertion

  • Scan architecture overview
  • Scan Design Basics
  • Scan Golden Rules
  • Scan DRC Checks
  • Scan Insertion
  • Generate test protocol and understanding
  • Lock-Up Latches

Module3: Scan Compression

  • Basics/Need for Compression
  • Compression Techniques
  • On-Chip-Clocking
  • At-Speed Testing

Module4: Hiearchical Scan And Boundary Scan

  • Hierarchical Scan
  • Bscan (Boundary Scan)
  • Jtag 1149.1

Module5: Introduction To ATPG, Atpg Basics

  • ATPG Basics
  • Faults Collapsing
  • ATPG Algorithms

Module6: Fault Models, Fault Classes

  • Fault Models,
  • ATPG Drc,
  • Fault Classes,
  • ATPG

Module7: Pattern Generation And Simulations

  • Simulation Basics
  • Atpg Simulations
  • Coverage Improvement

Module8: At- Speed ATPG And Simulations

  • At-Speed ATPG
  • LOC and LOS
  • At-Speed Simulations

Module9: Simulations And Debugging

  • Scan Simulations Debug
  • Diagonsis Flow
  • Fault Simulation

Module10: BIST

  • BIST Architecture,
  • Memory BIST
  • Logic BIST

Module11: Project

Tools to be used:

Synopsys DFT tool suite will be used, with one dedicated license for each trainee.

  • DFT Compiler – For Scan Insertion
  • BSD Compiler – For Boundary Scan Insertion
  • TetraMax  — For ATPG  / pattern Generation
  • VCS  — For Simulations and Debugging

Additional Lab Hours through VPN, to enable you to spend more time on labs from home. This is on top of Trainer led lab sessions during Saturdays.


  • Certification from ChipEdge after successful completion of the course.


The trainer has 19+ years of VLSI Industry Experience, with substantial experience in DFT and currently working as a manager in a Product company. He is passionate about teaching & sharing his knowledge and mentored entry/mid-level engineers throughout his career.

  • Multiple evaluation tests both for performance in course subjects as well as readiness for physical design jobs and placement readiness.
  • Certification from Chipedge Technologies Private Limited, for  all eligible students, who meets course completion criteria, which includes attendance, completing the assignments, final written test, Final project assessment.  Grade will be given as per the performance in these tests.


Enquire Now
  • 5 MonthsDURATION:
  • 6th July 2020 STARTS FROM:

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