Training Delivery Model:
- Lecture & Lab sessions go hand in hand, like corporate training.
- Sessions will be interactive in nature.
Training Material & Certification:
- Hand outs of training material will be provided.
- Course completion certificate from ChipEdge.
- Course learning will be assessed as per Bloom’s Taxonomy.
- Certification and 2 credits (leading to MS degree) from Global University of Engineering, USA
Who Can Attend This Course:
- Engineers working in Embedded / Electronics (PCB designing, assembling, testing..) and interested to Change Career into VLSI industry for work satisfaction & Career growth.
- Layout Engineers (analog / std cell / memory ), who would like fill the gaps in understanding and strengthen the expertise.
- Interns / Entry level Layout Engineers, who have started working on layouts, but not received any formal training.
- Circuit Design Engineers (analog / std cell / memory) seeking to learn Layout.
- Engineers working in different domains of VLSI, but interested to pursue career in Custom Layout.
- Faculties working in Engineering Colleges / Universities, teaching VLSI subjects.
Good Knowledge on below topics is required. One need to refresh his/her knowledge thoroughly, before the course as these fundamentals are essential to the course, but not part of the course curriculum.
- Working knowledge of linux.
- Knowledge of digital Electronics fundamentals.
- Knowledge of CMOS fundamentals
- B.E / B.Tech in Electronics / Electrical / Instrumentation
- M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar
Course Content outline:
Basic steps of IC fabrication
CMOS IC fabrication
Deep Submicron Technology
Layout Editor Tool
Creating and managing libraries and cell.
Commands for Layout editing.
Commands for schematic editing.
Verification : DRC and LVS
Layout or Physical Implementation
Understanding the schematic symbols and parameters
Resistor, Capacitor layout techniques
Cmos and BiCMOS layout techniques
Standard Cell Layout
layout of Inverter, AND, OR, NAND, NOR, AOI, OAI, LATCH, FLOP,
common centriod, interdigitized and proximity matching.
Matching of Resistors, Capacitors
Matching of mos transistors
Complex Layout enemies
Power/Signal IR Drop
cross-talk and coupling
Deep Submicron Layout Issues
Shallow Trench Isolation (LOD)
Well Proximity Effect.
Analog and Mix signal Layout
single stage differential opamp layout
input pair, current mirrors and output stage.
two stage differential opamp layout
input pair, differential routing, Power routing, offset minimizing.
Why memory layout different than analog layout
Memory layout flow
Types of memory layout (SRAM/DRAM/ROM)
Introduction to SRAM memory layout
Fixing few manually created leaf-cell errors which impact
Impact of IR, EM and DFM .
SRAM memory design architecture
Words line and address line
SRAM rows and column design
Building blocks of SRAM
Memory Bit cell
Word line driver
Misc digital logic.
Pitch Calculation for blocks.
Assignments based on above theory.
Memory Layout practice
Row decoder layout
Sense amplifier layout
Drivers and Decoder layout
Analog Projects like LDO, Op-amp & other similar size projects will be executed in latest technology nodes.
On memory, trainees will be asked to do layout of one memory.
Std layouts will be done as part of labs & assignments. No separate project will be executed.
Tools to be used:
- Industry standard layout tools will be used.
- Additional Lab Hours through VPN, to enable you spend more time on labs from home. This is on top of Trainer led lab sessions during sundays.
Assessment & Certification:
- Course completion certificate from ChipEdge.
- At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
- Certification and credits leading to M.S degree from Global University of Engineering, USA.
Trainer is having 10+ years of VLSI Industry experience in various organizations and currently working with a product MNC company.
He had worked with product, IP based and Services based companies and has deep knowledge in different layout areas i.e. analog and mixed signal layout, digital and memory layout and standard Cell Layout.
Experienced on different technology nodes from 700nm to 28nm. worked on multiple designs on analog IP’s ADC, DAC, PLL , buffers and different classes of Amplifiers.
He is passionate about teaching and enjoys sharing his knowledge.
Investment Amount and Details:
It would be right investment on this high quality course, with high ROI (return on investment) considering good opportunities available for quality Analog Layout Jobs.
- Rs 55,000 (15% Service tax Extra)
- Early Bird Offer : 5% discount, till 11th Nov 2016
- Group Discount:
- 2% discount on total fee for 3 or more participants joining together.