ATPG and Simulations

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Course Overview:

This course covers different aspects of ATPG which includes,  fault types, fault modelling, how to generate patterns on scan inserted netlist, review test coverage, how to improve test coverage, pattern simulation, diagnose the failure logs.

Learning Outcome:

At the end of this course, the candidate will be able to:

  • Read in the netlist that has DFT logic inserted in it and along with the various SPF files in the ATPG EDA tool.
  • Build the ATPG model.
  • Run DRC checks on the design.
  • Generate patterns for stuck-at and at-speed models.
  • Review Test Coverage & do incremental ATPG.
  • Write-out the patterns.
  • Simulate the patterns
  • Diagnose failure logs provided by the ATE engineer.

Training Delivery Model:

  • Lecture & Lab sessions go hand in hand, like corporate training.
  • Sessions will be interactive in nature.

Training Material & Certification:

  • Hand outs of training material will be provided.
  • Course completion certificate from ChipEdge.
  • Course learning will be assessed as per Bloom’s Taxonomy.
  • Credits leading to M.S degree and Certification from Global University of Engineering, USA.

Who Can Attend This Course:

  • Entry level / Experienced DFT engineers, who want to learn DFT in a systematic way from fundamentals to techniques, Methodologies.
  • RTL Design, Verification, Synthesis, STA and Physical Design Engineers, CAD Engineers who need to understand DFT for effective integration into their respective design flows.
  • Application Engineers who need to understand DFT, for effective customer interactions & problem solving
  • Faculty working in Engineering Colleges, teaching VLSI subjects.
  • Anyone interested to learn basic to intermediate level of DFT concepts and tool flow.
  • (VLSI) students.


  • Knowledge of digital design.
  • Knowledge of ASIC / SOC design flow.
  • At least 1 year of work experience in ASIC or SOC Design Flow.
  • Prior knowledge of DFT is not required

More than 50% of course time on hands-on Labs, Project.  Each module has associated labs and practiced at end of lecture session as below.

Course Content outline:

Course Duration: 5 Weeks (Saturdays)


  • ASIC Flow
  • DFT Overview
  • DFT Flow
  • Understanding of Defects and Faults
  • Functional test Vs Structural Test
  • ATPG
  • Understanding of Silicon testing from Tester to gate level
  • Fault Detection
  • Faults and fault collapsing
  • ATPG algorithm

Week 2:

  • Fault models
  • Types of fault models
  • Different types of ATPG
  • Stuckat fault model with an example
  • Understanding of ATPG constraints
  • Understanding of SPF
  • ATPG DRC analysis [2-3 Live examples]
  • ATPG for Stuckat fault model
  • Test Coverage Vs Fault Coverage

Week 3:

  • Usage of ATPG Graphical schematic viewer
  • Analyzing feedback paths
  • ATPG pattern simulation flow
  • Stuckat pattern Simulation and  failure debugging
  • Analyzing ATPG faults
  • Coverage improvement techniques
  • ATPG pattern optimization

Week 4:

  • At speed fault models
  • Understanding Transition fault ATPG
  • ATPG setup for transition fault model
  • ATPG for Transition fault model
  • Timing exceptions in atspeed testing
  • Path delay fault modelling
  • On-Chip clock controller

Week 5:

  • Transition Pattern simulation
  • Transition pattern Simulation failure debugging
  • Introduction to Diagnosis
  • Diagnosis Flow
  • Analysing failure logs

Tools to be used:

  • Industry Standard DFT Tool set will be used.
  • Additional Lab Hours through VPN, to enable you spend more time on labs from home. This is on top of Trainer led lab sessions during sundays.

Assessment & Certification:

  • Course completion certificate from ChipEdge.
  • At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
  • 3 credit Course  leading to M.S degree and Certification from Global University of Engineering, USA.


The trainer has 10+ years of VLSI  industry Experience, with last 8 years exclusively in DFT and currently working as DFT lead for a services company.  He has worked for customers like Texas Instruments, Intel.

He is passionate in teaching & sharing his knowledge and mentored entry / mid level engineers throughout his career.

Investment Amount:

If a man empties his purse into his head, no one take it away from him. An investment in knowledge always pays best interest. Benjamen Franklin.

It would be right investment on this high quality course, with high ROI (return on investment) considering good opportunities available for experienced & quality DFT engineers.


  • ₹ 30,000* (*15% Service Tax Extra)
  • Group Discount:
  • 3% discount (Rs 900) on total fee for 3 or more participants joining together.