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ASIC Design Verification {Full Time}

Course Overview:

The ASIC Design Verification Full-time course is designed for students looking to get comprehensive training that cover all the topics needed to start in the VLSI industry as a Verification Engineer. The course is designed by keeping the latest industry requirements in mind and will be covered by trainers experienced in Verification. All the relevant concepts, the latest methodologies, the support functions required as well as placement specific coaching will be provided over the duration of the course. More than 50% of the time will be utilised for hands on training along with multiple projects.

Course Highlights:

  • Foundation courses on Digital Electronics and CMOS devices, to improve fundamentals.
  • Soft Skills training for the candidates to be Industry ready.
  • Expert Trainers with strong Industry Experience
  • Perl Scripting Language.
  • Advanced topics like Reuse and Formal Verification
  • Project management tools like Code Version Management, Bug Tracking, Automation etc.
  • Infrastructure designed to provide a fully corporate experience.
  • Individual attention to identify student weaknesses and help improve on them.
  • Opportunity to absorb the knowledge and experiences of experts from the industry.

Training Delivery Model:

  • Instructor led classroom training sessions from 9.30 am to 5.00 pm – Mondays to Fridays
  • Each topic is followed by Lab sessions on that particular module.
  • 24/7 remote Lab access through VPN.
  • Closed group support with Trainers and Lab Assistants on WhatsApp and e-mail.

Training Materials:

  • Physical Handouts of Training Materials will be provided to all students.
  • Integrated Online Learning Management System where all reference materials and performance tracking will be available for every student.
  • Multiple evaluation tests both for performance in course subjects as well as self-evaluation for placement readiness.

Who are eligible for the course

      • Graduate Freshers in Electronics & Communication Engineering(BE/B.Tech)who have graduated in or after 2016 looking to start their careers in VLSI as a Verification Engineer.
      • Post-Graduate Freshers in Electronics & Communication Engineering (M.Tech) with specializations like VLSI, Instrumentation and Embedded Systems etc. who have graduatedin or after 2016.
      • Experienced graduates/post-graduates with the above mentioned qualifications who wish to change into the VLSI Verification domain.

Selection Criteria

ChipEdge follows a comprehensive selection criterion for all candidates. Candidates, especially freshers are selected considering their prior academic performances, knowledge of fundamentals and ability to perform successfully in placement interviews. The selection process consists of

      • General Evaluation Test – Covering fundamentals required for the VLSI industry as well as Aptitude.
      • Face to Face interviews with all candidates.

Course Outline:

 

Module 1

  • Basic design support systems –Unix/Linux, Text editors.
  • Perl Scripting Language

Module 2

  • Digital Fundamentals
  • Digital Design

Module 3

  • HDL(Verilog)
  • HDL for design, Verification.
  • Designing using HDL

Module 4

  • Designing for synthesis.
  • Basic Checks on the HDL code.

Module 5:

  • Design from Spec.
  • Design support tools – Code version management.
  • Basic Verification flow and associated planning.
  • Mini Project – Design verification.
  • Design support tools – Bug tracking.
  • Debug techniques.

Module 6:

  • System Verilog – Basic
  • System Verilog for Verification
  • System Verilog Verification project

Module 7:

  • UVM Basics
  • Automation in verification
  • UVM Advanced
  • UVM – Mini Project

Module 8:

  • Course ending project
  • Gate Level simulations and Challenges.
  • Advanced topics
    • Formal Verification
    • Potable Simulations
    • Importance of Emulation
    • Low power verification techniques
  • Guest Lectures

Module 9

  • Soft skills

 

 

Tools to be used:

  • Simulation based verification tools from industry leading vendor.
  • Static design checker/verification tools

Trainer:

  • Lead trainer is an experienced Verification Engineer in a leading Verification Services company.
  • Additional trainer is an experienced teacher, with a rich experience of teaching and mentoring entry level engineer students. Her passion and dynamism had led to excellent feedback from her students with many going on to have a very successful professional career.

 

Soft skills training by leading corporate soft skill trainers.

Certifications:

  • Certification from Chipedge Technologies Private Limited.
  • Course learning assessment will be based on Blooms Taxonomy.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

 

 

 

 

 

Lessons