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ASIC DESIGN VERIFICATION – FULL TIME
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Analog Layout Design
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Synthesis, Sign off STA and LEC
CMOS Analog Circuit Design
Verification Using UVM
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VLSI COURSES
For Freshers
ASIC DESIGN VERIFICATION – FULL TIME
PHYSICAL DESIGN – FULL TIME
For Freshers and Professionals
ASIC Design Verification
Physical Design
Design For Test (DFT)
Analog Layout Design
For Professionals
Synthesis, Sign off STA and LEC
CMOS Analog Circuit Design
Verification Using UVM
Verification Using System Verilog
Online
ANALOG CIRCUIT DESIGN
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ANALOG CIRCUIT DESIGN – ONLINE
ANALOG CIRCUIT DESIGN – ONLINE
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6 weeks
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November 2019
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6 weeks
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24
th
November 2019
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Time Duration
36 hours
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Analog Layout Design
ASIC Design Verification
SYNTHESIS SIGN-OFF STA AND LEC
Design For Test (DFT)
Physical Design
ASIC DESIGN VERIFICATION {FULL TIME}
VERIFICATION USING UVM
CMOS ANALOG CIRCUIT DESIGN
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