Congratulations to Anushree Chandran for placement in Synopsys in Physical Design    Congratulations to Bandreddi Venkateshwar Rao and Kishor Naik for placement in Aricent in Physical Design    Congratulations to Chaitrashree and Prathamesh Kulkarni for placement in JGD Tech in Analog Layout    Congratulations to Hemavathy and Suman for placement in Aricent in Physical Design    Congratulations to Jagan for placement in Wipro in Physical Design    Congratulations to Jithesh for placement in Laksh Semi in Physical Design    Congratulations to Juturu Muruli Shankar and Shreyas BK for placement in Aricent in Physical Design    Congratulations to Shubha for placement in Sibot Technologies in Analog Layout    Congratulations to Manoj Chowdary and Payam Nagesh for placement in Aricent in Physical Design    Congratulations to Neeraj Sharma for placement in Black Pepper in Analog Layout    Congratulations to Podila Keerthi and Praveen Chennam for placement in Aricent in Physical Design    Congratulations to Navyatha for placement in Altran in Physical Design    Congratulations to Sneha Rathod for placement in Exiger in Physical Design    Congratulations to Surabhi and Abhishek for placement in Aricent in Physical Design

ChipEdge is unique in offering wide range of high quality Skill Development / Enhancement instructor led class room VLSI courses during weekends. Our course offering covers complete front end & back end flows across Digital and Analog domains.

Upcoming VLSI Courses Calendar

30-06-2018
CMOS Analog Circuit Design

Duration: 08 Weeks(Sat)

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14-07-2018
Verification using System Verilog

Duration: 06 Weeks(Sat)

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28-07-2018
Physical Design

Duration: 12 Weeks(Sat)

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29-07-2018
DFT (SCAN & ATPG)

Duration: 10 Weeks(Sun)

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18-08-2018
TCL Scripting

Duration: 03 Weeks(Sat)

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25-08-2018
ASIC Design Verification

Duration: 15 Weeks(Sat)

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25-08-2018
Synthesis Sign-Off STA and LEC

Duration: 07 Weeks(Sat)

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25-08-2018
Verification using UVM

Duration: 05 Weeks(Sat)

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16-09-2018
Analog Layout Design and Physical Verification

Duration: 12 Weeks(Sun)

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30-09-2018
Low Power Implementation(PD) using UPF

Duration: 4 Weeks(Sun)

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29-09-2018
High Speed IO Circuit Design

Duration: 08 Weeks(Sat)

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Highlights:

  • Trainers with rich (10-20 years) industry experience, currently working in the industry on latest technologies. They are very passionate to teach and excellent teaching skills.
  • Training with Industry standard tools, like Synopsys.
  • Certification and Course Credits leading to M.S. degree, from Global University of Engineering, USA
  • Additional lab hours through VPN, with 24×7 access.
  • Course designed by experts, as per the technical Skill requirements of Semiconductor Industry.
  • 50 to 70% of time on labs, to facilitate more hands on learning using tools.
  • Labs, Projects on latest technology nodes.
  • Cost effective and value for money, with good ROI (Return on Investment) through Career Growth.