All You Need to Know About Netlist in VLSI!

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All You Need to Know About Netlist in VLSI!

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Netlist contains the electrical connections between the components on the circuit board and is usually held in a textual format. In an electronic circuit netlist is the description of the connectivity of an electronic circuit it contains the list of all the electronic components in a circuit and the nodes they are connected to circuits. A net or network is a collection of two or more interconnected components in an electronic design. 

RTL Netlist vs Synthesized Netlist 

The RTL code of design module is transformed into gate level netlist through the process of synthesis. Synthesis is the most curricular step in chip designing among all other steps.  At the synthesis process one can visualize the designs which will appear after manufacturing. The functionality of a device written in a language such as verilog or VHDL is called RTL. If it can be synthesized to convert into gate level description. After synthesizing a RTL we get a netlist which is the gate level description of the device.


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Flat Level Netlist vs Hierarchical Netlist 

Flat networks are designed to reduce the number of switches in a computer or design. It has a single device which connects the rest of the components.The debugging capacities are limited in a flat netlist, additionally synthesis tool can be used to optimize the circuit better.

In a hierarchical design the design is separated using different switches. Moreover, the hierarchical  network is separated into distinct layer switches each later performs a series of functions which defines its role in the network.

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