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A View On: The Types of Variation

A View On: The Types of Variation

What Is The Variation Law?

The Law of Variation characterizes the difference between an ideal and a real condition. The most common occurrences of variation or variability are the different types of variations in data, predicted results, or minor changes in manufacturing quality. All types of variations can be seen in four different areas:

  1. Special reasons
  2. Causes that are common
  3. Tampering
  4. Variation in structure

VLSI On-Chip Variation: Physical Design On-Chip Variation

The.gds (Graphical Design System) file is the last output that travels to the fabrication facility following VLSI physical design and signoff in the ASIC design cycle. Based on this final gds data, an IC (Integrated Circuit) is built on a silicon wafer. A large silicon wafer is split into many tiny die. Each of the dies has an individual integrated circuit. We cut and separate each die after wafer-level testing and execute IC packaging.

We have the identical gds data for all ICs in all dies, but the die position on the wafer is different. If all of the dies have the same gds, then all of the ICs should have the same electrical properties. However, this is not the case practically. The electrical properties of ICs made on various dies, varies.

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What Are The Sources of Different Types of Variations?

Process, voltage, and temperature are the three primary drivers of different types of variations. All these variations are collectively called PVT variations. The question may arise in your mind: if we already undertake PVT analysis and account for the different types of variations when developing an ASIC, then why do we need to worry about On-Chip Variation separately.

Well, the explanation is that PVT analysis cannot account for all possible types of variation. Some of them are predictable. And as technology advances, they can be easily simulated whereas others are very unexpected and difficult to model.

What Are The Types Of Variation?

Process Variations:

When integrated circuits are created, process variation is one of the naturally occurring types of variations in the properties of transistors (lengths, widths, and oxide thickness). As the variation becomes a larger percentage of the full length or width of the device, the amount of process variation becomes particularly pronounced at smaller process nodes (65 nm).

Because of mismatch, process variation produces observable and predictable change in the output performance of all circuits, especially analogue circuits. The total yield for that collection of devices is reduced if the variation causes the measured or simulated performance of a given output metric (bandwidth, gain, rise time, etc.) to fall below or rise above the specification for that circuit or device.

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There are two forms of process variation:

  • Systematic variation and
  • Non-systematic variation, also known as random variation.

Optical Proximity Corrections (OPC) or Chemical Mechanical Policing (CMP) cause systematic changes. Random Dopant Fluctuation (RDF), Line Edge Roughness (LER), and Oxide Thickness Fluctuations (OTV) are non-systematic variations that are very unexpected and difficult to model. Alternatively, one may claim that these types of variations occur randomly in nature.

One type of voltage variation is caused by changes in the external supply voltage, while the other is caused by changes in the internal voltage of the chip.

Temperature Variations:

Transistors’ properties greatly rely on the junction temperature. The application of ASIC in PVT takes into account the ambient temperature. However, the chip architecture determines the temperature of the junction. Power dissipation inside the chip might raise the temperature of neighboring junctions, affecting the chip’s overall performance.

What Are The Effects of On-Chip Variation?

If not addressed during ASIC design, On-Chip Variation can lead to post-silicon failure. OCV may lead to a setup time violation in all circumstances. A similar situation may arise in the case of the hold time. If we don’t take care of On-Chip Variation, a correct timing closure chip may violate the timing and fail.

Know more in detail about types of variations by enrolling in a course on Chipedge which is the best VLSI training institute in India for online VLSI trainingThere are several online VLSI courses on this website for starting a successful career in VLSI industry.

Read more- What are the EDA tools in VLSI

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